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Application Note 50
Implementing the RC5050 and RC5051 DC-DC
®
Converters on Pentium Pro Motherboards
Introduction Intel Pentium Pro Processor Power
Requirements
This document describes how to implement a switching volt-
®
age regulator using an RC5050 or an RC5051 high speed
Refer to Intel’s AP-523 Application Note, Pentium Pro
controller, a power inductor, a Schottky diode, appropriate
Processor Power Distribution Guidelines, November 1995
capacitors, and external
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AN50 APPLICATION NOTE ® Table 2. Intel Pentium Pro and OverDrive Processor Power Specifications Voltage Maximum Maximum Thermal 1 Specification, Current, Design power CPU Model, Features V P (VDC) I P (A) (W) CC CC 150MHz, 256K L2 Cache 3.1 – 5% 9.9 29.2 166MHz, 512K L2 Cache 3.3 – 5% 11.2 35.0 180MHz, 256K L2 Cache 3.3 – 5% 10.1 31.7 200MHz, 256K L2 Cache 3.3 – 5% 11.2 35.0 200MHz, 512K L2 Cache 3.3 – 5% 12.4 37.9 OverDrive Processors 150Mhz 2.5 – 5% 11.2 26.7 180Mhz 12.5 29.7 200Mhz 13.9 32.9 2
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APPLICATION NOTE AN50 I/O Controls The RC5050 and RC5051 Controllers In addition to the Voltage Identification, there are several sig- The RC5050 is a programmable non-synchronous DC-DC nals that control the DC-DC converter or provide feedback controller IC. The RC5051 is a synchronous version of the from the DC-DC converter to the CPU. They are Power- RC5050. When designed around the appropriate external Good (PWRGD), Output Enable (OUTEN), and Upgrade components, either of these devices ca
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AN50 APPLICATION NOTE +12V RC5051 +5V OSC – + – + DIGITAL VO CONTROL 1.24v 5-BIT VREF REFERENCE DAC POWER GOOD PWRGD 65-5051-01 VID0 VID2 RSEL VID1 VID3 Figure 2. RC5051 Block Diagram The HIDRV driver has a power supply, VCCQP, supplied age and outputs an active-low interrupt signal to the CPU from a 12V source as illustrated in Figure 2. The resulting when the power supply voltage exceeds – 12% of nominal. voltage is sufficient to provide the gate to source voltage to The Power Good flag provi
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APPLICATION NOTE AN50 In general, a lower operating frequency decreases the peak Short Circuit Protection ripple current flowing in the output inductor, thus allowing A current sense methodology is implemented to disable the the use of a smaller inductor value. Unfortunately, operation output drive signal to the MOSFET(s) when an over-current at lower frequencies increases the amount of energy storage condition is detected. The voltage drop created by the output that must be provided by
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AN50 APPLICATION NOTE +12V L2 +5V 2.5 μH C5 C4 C3 C1 C2 R5 0.1 μF 1000 μF 1000 μF 1000 μF 0.1μF 47 D1 C9 C8 1N4691 0.1 μF 0.1μF M1 M2 C12 IRF7413 11 10 9 1μF 12 IRF7413 R L1 SENSE 8 13 C6 VO 14 7 1.3μ H 6m Ω 15 6 4.7 F μ RC5051 16 5 VREF DS1 17 4 1N5817 C7 18 3 M3 M4 19 2 0.1 μF IRF7413 IRF7413 20 1 GND C EXT 100pF VID4 VCC VID3 R6 10K VID2 PWRGD VID1 C11 ENABLE 0.1μF VID0 C10 0.1μF Figure 4. Synchronous DC-DC Converter Application Schematic Using the RC5051 6 C13 1500 μF C14 1500 μF C15 1500
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APPLICATION NOTE AN50 MOSFET Selection Cosiderations • Power package with low Thermal Resistance • Drain current rating of 20A minimum MOSFET Selection • Drain-Source voltage > 15V. This application requires N-channel Logic Level Enhance- ment Mode Field Effect Transistors. Desired characteristics The on-resistance (R ) is the primary parameter for DS,ON are as follows: MOSFET selection. It determines the power dissipation within the MOSFET and, therefore, significantly affects the • Low St
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AN50 APPLICATION NOTE Two MOSFETs in parallel. +5V We recommend two MOSFETs used in parallel instead of one single MOSFET. The following significant advantages DS2 are realized using two MOSFETs in parallel: VCCQP M1 • Significant reduction of Power dissipation. HIDRV Maximum current of 14A with one MOSFET: L1 RS CP VO PWM/PFM 2 Control P = (I R )(Duty Cycle) = MOSFET DS,ON 2 CB DS1 (14) (0.050*)(3.3+0.4)/(5+0.4-0.35) = 7.2 W With two MOSFETs in parallel: 65-AP50-01 2 P = (I R )(Duty Cycle)
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APPLICATION NOTE AN50 Converter Efficiency Losses due to parasitic resistance in the switches, coil, and • gate-charge losses sense resistor dominate at high load-current level. The major • diode-conduction losses loss mechanisms under heavy loads, in usual order of impor- • transition losses tance, are: • Input Capacitor losses • losses due to the operating supply current of the IC. 2 • MOSFET I R Losses • Coil Losses • Sense Resistor Losses Calculation of Converter Efficiency Under Heavy Loads
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AN50 APPLICATION NOTE When designing the external current sense circuitry, pay Selecting the Inductor careful attention to the output limitations during normal The inductor is one of the most critical components to be operation and during a fault condition. If the short circuit selected for a DC-DC converter application. The critical protection threshold current is set too low, the DC-DC con- parameters are inductance (L), maximum DC current (I ), O verter may not be able to continuously d
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APPLICATION NOTE AN50 Therefore, for load current of 14.5A, the peak current The next step is to determine the value of the sense resistor. through the inductor, I , is found to be approximately Including sense resistor tolerance, the sense resistor value pk 15.5A: can be approximated as follows V V (I – I ) th,min th,min PK min ---------------- ---------------------------------- - R = · (1 – TF) = · (1 – TF) = + ----------------------------- = 14.5 + 2 = 16.5A SENSE I ‡ I I SC inductor Load
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AN50 APPLICATION NOTE Embedded Sense Resistor (PC Trace Resistor) where: Embedded PC trace resistors have the advantage of near zero r = Resistivity(mW -mil), cost implementation. However, the value of the PC trace L L = Length(mils), resistor has large variations. Embedded resistors have 3 W W = Width(mils), and t major error sources: the sheet resistivity of the inner layer, t = Thickness(mils). the mismatch due to L/W, and the temperature variation of For 1oz copper, t = 1.35 mils, r = 71
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APPLICATION NOTE AN50 Embedded Sense Resistor IFBH MnCu Discrete Resistor R21 R22 IFBL Output Power Plane (Vout) R-Δr R R+Δr Figure 11. Short Circuit Sense Resistor Design Using a PC Trace Resistor and an Optional Discrete Sense Resistor tion. The embedded sense resistor allows the user to choose a Power Dissipation Consideration During a plus or a minus delta resistance tap to offset any large sheet Short Circuit Condition resistivity change. In this design, the center tap yields 6mW , Th
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AN50 APPLICATION NOTE P = I · V · (1 – DutyCycle) = D, Diode F, ave F 14 · 0.45 · 0.8 » 5W Thus, for the Schottky diode, the thermal dissipation during a short circuit is greatly magnified. This requires that the thermal dissipation of the diode be properly managed by an appropriate heat sink. To protect the Schottky from being destroyed in the event of a short circuit, you should limit the junction temperature to less than 130 C. You can find the required thermal resistance using the equ
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APPLICATION NOTE AN50 FET. Low Equivalent Series Resistance (ESR) capacitors are For I = 12.2A (0-13A load step) and D V = 100mV, the bulk O best suited for this type of application. Incorrect selection capacitance required can be approximated as follows: can hinder the converter's overall performance. The input I · D T O 12.2A · 2m s capacitor should be placed as close to the drain of the FET as C(m F) = ------------------------------------- -= --------------------------------------------
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AN50 APPLICATION NOTE Table 11. Bill of Materials for a 13A Pentium Pro Klamath Application (continued) Quantity Reference Manufacturer Part Description Requirements and Order # Comments 1 L1 Pulse Engineering 1.3m H inductor PE-53680 1 L2* Pulse Engineering 2.5m H inductor *Optional—helps PE-53681 reduce ripple on 5v line 2-4 M1-M4 International Rectifier N-Channel Logic Level R < 18mW DS,ON (note 2) IRF7413 Enhancement Mode MOSFET V = 4.5V, I = 5A GS D 1 Rsense Coppel 6 mW , 1W CuNi Wire r
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APPLICATION NOTE AN50 In general, all of the noisy switching lines should be kept • Place the output bulk capacitors as close to the CPU as away from the quiet analog section of the RC5050. That is, possible to optimize their ability to supply instantaneous traces that connect to pins 12 and 13 (HIDRV and current to the load in the event of a current transient. VCCQP) should be kept far away from the traces that con- Additional space between the output capacitors and the nect to pins 1 thr
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AN50 APPLICATION NOTE 9. Next, look at HIDRV pin. This pin directly drives the Guidelines for Debugging and gate of the FET. It should provide a gate drive (Vgs) of Performance Evaluations about 5V when turning the FET on. A careful study of the layout is recommended. Refer to the “PCB Layout Debugging Your First Design Implementation Guidelines” section. 1. Note the setting of the VID pins to know what voltage is to be expected. 10. Past experience shows that the most frequent errors are
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APPLICATION NOTE AN50 Output Voltage Load Transients Due to Load Current Step VID I (A) V (V) load out This test is performed using Intel P6.0/P6S/P6T Voltage 11010 0.5 2.505 Transient Tester. 1.0 2.504 Low to High 0.5A-9.9A -76.0mV Refer to 2.0 2.501 Current Step Attachment 3.0 2.496 A for Scope 4.0 2.493 Picture 5.0 2.493 High to Low 9.9A-0.5A +70mV Refer to Current Step Attachment 6.0 2.492 B for Scope 7.0 2.492 Picture 8.0 2.491 Low to High 0.5A-12.4A -97.6mV Refer to 9.0 2.490 Cur
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AN50 APPLICATION NOTE Input Ripple and Power on Input Rush Current Power on Input Rush Current was not measured on the moth- erboard because we did not want to cut the 5V trace and insert a current probe in series with the supply. However, I = 9.9A Input Ripple Refer to Attach- load with the input filter design, the Input Rush Current is well Voltage = 15mV ment G for Scope within specification. Picture Note: Excellent input ripple voltage. Input ripple voltage is recom- mended to be less tha
