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TECHNICAL
MANUAL
LSI53C875A
PCI to Ultra SCSI
Controller
Version 2.0
December 2000
®
S14047
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This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation. LSI Logic products are not intended for use in life-support appliances, devices, or systems. Use of any LSI Logic product in such applications without written consent of the appropriate LSI Logic officer is prohibited. Document DB14-000143-01, Second Edition (Dece
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Preface This book is the primary reference and technical manual for the LSI53C875A PCI to Ultra SCSI Controller. It contains a complete functional description for the product and also includes complete physical and electrical specifications. Audience This manual provides reference information on the LSI53C875A PCI to Ultra SCSI Controller. It is intended for system designers and programmers who are using this device to design an Ultra SCSI port for PCI-based personal computers, workstations, ser
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• Chapter 6, Electrical Specifications contains the electrical characteristics and AC timing diagrams. • Appendix A, Register Summary is a register summary. • Appendix B, External Memory Interface Diagram Examples contains several example interface drawings for connecting the LSI53C875A to external ROMs. Related Publications For background information, please contact: ANSI 11 West 42nd Street New York, NY 10036 (212) 642-4900 Ask for document number X3.131-199X (SCSI-2) Global Engineering Docume
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PCI Special Interest Group 2575 N.E. Katherine Hillsboro, OR 97214 (800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344 Conventions Used in This Manual The word assert means to drive a signal true or active. The word deassert means to drive a signal false or inactive. Hexadecimal numbers are indicated by the prefix “0x” —for example, 0x32CF. Binary numbers are indicated by the prefix “0b” —for example, 0b0011.0010.1100.1111. Revision Record Revision Date Remarks Preliminary 5/00 Pr
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vi Preface
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Contents Chapter 1 General Description 1.1 New Features in the LSI53C875A 1-3 1.2 Benefits of Ultra SCSI 1-3 ® 1.3 TolerANT Technology 1-4 1.4 LSI53C875A Benefits Summary 1-4 1.4.1 SCSI Performance 1-5 1.4.2 PCI Performance 1-6 1.4.3 Integration 1-6 1.4.4 Ease of Use 1-6 1.4.5 Flexibility 1-7 1.4.6 Reliability 1-8 1.4.7 Testability 1-8 Chapter 2 Functional Description 2.1 PCI Functional Description 2-2 2.1.1 PCI Addressing 2-2 2.1.2 PCI Bus Commands and Functions Supported 2-3 2.1.3 PCI Cache Mo
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2.2.11 Parity Options 2-24 2.2.12 DMA FIFO 2-27 2.2.13 SCSI Bus Interface 2-32 2.2.14 Select/Reselect During Selection/Reselection 2-33 2.2.15 Synchronous Operation 2-34 2.2.16 Interrupt Handling 2-37 2.2.17 Chained Block Moves 2-44 2.3 Parallel ROM Interface 2-48 2.4 Serial EEPROM Interface 2-50 2.4.1 Default Download Mode 2-50 2.4.2 No Download Mode 2-51 2.5 Power Management 2-51 2.5.1 Power State D0 2-52 2.5.2 Power State D1 2-52 2.5.3 Power State D2 2-53 2.5.4 Power State D3 2-53 Chapter 3 S
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Chapter 4 Registers 4.1 PCI Configuration Registers 4-1 4.2 SCSI Registers 4-18 4.3 64-Bit SCRIPTS Selectors 4-99 4.4 Phase Mismatch Jump Registers 4-103 Chapter 5 SCSI SCRIPTS Instruction Set 5.1 Low Level Register Interface Mode 5-1 5.2 High Level SCSI SCRIPTS Mode 5-2 5.2.1 Sample Operation 5-3 5.3 Block Move Instruction 5-6 5.3.1 First Dword 5-6 5.3.2 Second Dword 5-13 5.4 I/O Instruction 5-13 5.4.1 First Dword 5-14 5.4.2 Second Dword 5-21 5.5 Read/Write Instructions 5-22 5.5.1 First Dword 5
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6.3 AC Characteristics 6-9 6.4 PCI and External Memory Interface Timing Diagrams 6-11 6.4.1 Target Timing 6-13 6.4.2 Initiator Timing 6-19 6.4.3 External Memory Timing 6-35 6.5 SCSI Timing Diagrams 6-52 6.6 Package Diagrams 6-58 Appendix A Register Summary Appendix B External Memory Interface Diagram Examples Index Customer Feedback Figures 1.1 Typical LSI53C875A System Application 1-2 1.2 Typical LSI53C875A Board Application 1-2 2.1 LSI53C875A Block Diagram 2-2 2.2 Parity Checking/Generation 2-
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6.9 PCI Configuration Register Read 6-13 6.10 PCI Configuration Register Write 6-14 6.11 32-Bit Operating Register/SCRIPTS RAM Read 6-15 6.12 64-Bit Address Operating Register/SCRIPTS RAM Read 6-16 6.13 32-Bit Operating Register/SCRIPTS RAM Write 6-17 6.14 64-Bit Address Operating Register/SCRIPTS RAM Write 6-18 6.15 Nonburst Opcode Fetch, 32-Bit Address and Data 6-20 6.16 Burst Opcode Fetch, 32-Bit Address and Data 6-22 6.17 Back-to-Back Read, 32-Bit Address and Data 6-24 6.18 Back-to-Back Writ
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B.3 128 Kbytes, 256 Kbytes, 512 Kbytes, or 1 Mbyte Interface with 150 ns Memory B-3 B.4 512 Kbyte Interface with 150 ns Memory B-4 Tables 2.1 PCI Bus Commands and Encoding Types for the LSI53C875A 2-4 2.2 PCI Cache Mode Alignment 2-12 2.3 Bits Used for Parity Control and Generation 2-25 2.4 SCSI Parity Control 2-26 2.5 SCSI Parity Errors and Interrupts 2-26 2.6 Parallel ROM Support 2-49 2.7 Mode A Serial EEPROM Data Format 2-51 2.8 Power States 2-52 3.1 LSI53C875A Internal Pull-ups 3-3 3.2 Syste
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5.2 SCSI Information Transfer Phase 5-12 5.3 Read/Write Instructions 5-24 5.4 Transfer Control Instructions 5-26 5.5 SCSI Phase Comparisons 5-29 6.1 Absolute Maximum Stress Ratings 6-2 6.2 Operating Conditions 6-2 6.3 Input Capacitance 6-2 6.4 Bidirectional Signals—MAD[7:0], MAS/[1:0], MCE/, MOE/, MWE/ 6-3 6.5 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/, GPIO[2:4] 6-3 6.6 Bidirectional Signals—AD[31:0], C_BE[3:0]/, FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR 6-4 6.7 Input Signals—CLK,
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6.30 External Memory Write 6-38 6.31 Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Read Cycle 6-42 6.32 Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access Write Cycle 6-43 6.33 Slow Memory (≤ 128 Kbytes) Read Cycle 6-48 6.34 Slow Memory (≤ 128 Kbytes) Write Cycle 6-49 6.35 ≤=64 Kbytes ROM Read Cycle 6-50 6.36 ≤ 64 Kbyte ROM Write Cycle 6-51 6.37 Initiator Asynchronous Send 6-52 6.38 Initiator Asynchronous Receive 6-53 6.39 Target Asynchronous Send 6-54 6.40 Target Asynchronous Receive 6
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Chapter 1 General Description Chapter 1 is divided into the following sections: • Section 1.1, “New Features in the LSI53C875A” • Section 1.2, “Benefits of Ultra SCSI” ® • Section 1.3, “TolerANT Technology” • Section 1.4, “LSI53C875A Benefits Summary” The LSI53C875A PCI to Ultra SCSI Controller brings Ultra SCSI performance to host adapter, workstation, and general computer designs, making it easy to add a high-performance SCSI bus to any PCI system. It supports Ultra SCSI transfer rates with Si
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Figure 1.1 Typical LSI53C875A System Application SCSI Bus PCI Bus PCI Bus LSI53C875A Fixed Disk, Optical Disk Interface PCItoWideUltra Printer, Tape, and Other Controller SCSI Controller Peripherals PCI Graphic Accelerator PCI Fast Ethernet Memory Controller Central Typical PCI Processing Computer System Unit Memory Architecture (CPU) Figure 1.2 Typical LSI53C875A Board Application Memory Memory Control SCSI Data, Address/Data Block Parity and Bus Control 68 Pin Flash EEPROM Signals SCSI LSI53C8
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1.1 New Features in the LSI53C875A The LSI53C875A is a drop-in replacement for the LSI53C875 PCI to Ultra SCSI Controller, with these additional benefits: • Supports 32-bit PCI Interface with 64-bit addressing. • Handles SCSI phase mismatches in SCRIPTS without interrupting the CPU. • Supports JTAG boundary scanning. • Supports PC99 Power Management. – Automatically downloads Subsystem Vendor ID, Subsystem ID, and PCI power management levels D0, D1, D2, and D3. • Improves PCI bus efficiency thro
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synchronous negotiations for Ultra SCSI rates and to enable the clock quadrupler. Chapter 2, “Functional Description,” contains more information on Ultra SCSI design. ® 1.3 TolerANT Technology The LSI53C875A features TolerANT technology, which includes active negation on the SCSI drivers and input signal filtering on the SCSI receivers. Active negation actively drives the SCSI Request, Acknowledge, Data, and Parity signals HIGH rather than allowing them to be passively pulled up by terminators.
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• Ease of Use • Flexibility • Reliability • Testability 1.4.1 SCSI Performance To improve SCSI performance, the LSI53C875A: • Has integrated SE transceivers. • Bursts up to 512 bytes across the PCI bus through its 944 byte FIFO. • Performs wide, Ultra SCSI synchronous transfers as fast as 40 Mbytes/s. • Can handle phase mismatches in SCRIPTS without interrupting the system processor, eliminating the need for CPU intervention during an I/O disconnect/reselect sequence. • Achieve Ultra SCSI transf
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• Supports additional arithmetic capability with the Expanded Register Move instruction. 1.4.2 PCI Performance To improve PCI performance, the LSI53C875A: • Complies with PCI 2.2 specification. • Supports 32-bit 33 MHz PCI interface with 64-bit addressing. • Supports dual address cycles which can be generated for all SCRIPTS for > 4 Gbyte addressability. • Bursts 2, 4, 8, 16, 32, 64, or 128 Dword transfers across the PCI bus. • Supports 32-bit word data bursts with variable burst lengths. • Pref
