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SME5224AUPA-400
July 1999
™
UltraSPARC -II CPU Module
400 MHz CPU, 4.0 MB E-Cache
DATASHEET
MODULE DESCRIPTION
The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400) delivers high performance
computing in a compact design. Based on the UltraSPARC™-II CPU, this module is designed using a small
form factor board with an integrated external cache. It connects to the high bandwidth Ultra™ Port Architec-
ture UPA bus via a high speed sturdy connector. The UltraSPARC™–II, 400 MHz CPU, 4.
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™ UltraSPARC -II CPU Module SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache CPU DESCRIPTION UltraSPARC-II CPU The UltraSPARC™-II CPU is the second generation in the UltraSPARC™ s-series microprocessor family. A complete implementation of the SPARC V9 architecture, it has binary compatibility with all previous ver- sions of the SPARC™ microprocessor family. The UltraSPARC™-II CPU is designed as a cost effective, scalable and reliable solution for high-end worksta- tions and servers. Meeting the dema
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™ UltraSPARC -II CPU Module Advanced Version 400 MHz CPU, 4.0 MB E-Cache SME5224AUPA-400 DATA BUFFER DESCRIPTION UltraSPARC-II Data Buffer (UDB-II) The UltraSPARC™-II module has two UltraSPARC-II data buffers (UDB-II) - each a 256 pin BGA device - for a UPA Interconnect system bus width of 128 Data + 16 ECC. There is a bidirectional flow of information between the external cache of the CPU and the 144-bit UPA inter- connect. The information flow is linked through the UDB-II, it includes: cache fill
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™ UltraSPARC -II CPU Module SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache MODULE COMPONENT OVERVIEW The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400), (see Figure 1), consists of the following components: • UltraSPARC™-II CPU at 400 MHz • UltraSPARC-II Data Buffer (UDB-II) • 4.0 Megabyte E-cache, made up of eight (256K X 18) data SRAMs and one 128K X 36 Tag SRAM • Clock Buffer: MC100LVE210 • DC-DC regulator (2.6V to 1.9V) • Module Airflow Shroud Block Diagram The module block dia
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™ UltraSPARC -II CPU Module Advanced Version 400 MHz CPU, 4.0 MB E-Cache SME5224AUPA-400 SYSTEM INTERFACE [1] Figure 2 shows the major components of a UPA based uniprocessor system. The system controller for the UPA bus arbitrates between the UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, and the I/O bridge chip. The figure also illustrates a slave-only UPA graphics port for Sun graphics boards. The module UPA system interface signals run at one-quarter of the rate of the internal CPU frequency.
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™ UltraSPARC -II CPU Module SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache Module ID Module IDs are used to configure the UPA address of a module. The UPA_PORT_ID[4:3] are hardwired on the module to “0”. UPA_PORT_ID[1:0] are brought out to the connector pins. Each module is hardwired in the system to a fixed and unique UPA address. This feature supports systems with four or fewer processors. For systems that need to support eight modules, UPA_SPEED[1] is connected to SYSID[2] in UDB-II to pro- vide U
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™ UltraSPARC -II CPU Module Advanced Version 400 MHz CPU, 4.0 MB E-Cache SME5224AUPA-400 [1] SIGNAL DESCRIPTION System Interface Signal Type Name and Function UPA_ADDR[35:0] I/O Packet switched transaction request bus. Maximum of three other masters and one system controller can be connected to this bus. Includes 1-bit odd-parity protection. Synchronous to UPA_CLK. UPA_ADDR_VALID I/O Bidirectional radial UltraSPARC-II Bus signal between the UltraSPARC-II CPU and the system. Driven by UltraSPARC-
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™ UltraSPARC -II CPU Module SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache JTAG/Debug Interface Signal Type Name and Function TDO O IEEE 1149 test data output. A three-state signal driven only when the TAP controller is in the shift-DR state. TDI I IEEE 1149 test data input. This pin is internally pulled to logic one when not driven. TCK I IEEE 1149 test clock input. This pin if not hooked to a clock source must always be driven to a logic 1 or a logic 0. TMS I IEEE 1149 test mode select input. Thi
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™ UltraSPARC -II CPU Module Advanced Version 400 MHz CPU, 4.0 MB E-Cache SME5224AUPA-400 UPA AND CPU CLOCKS Module Clocks The module receives three differential pair low voltage PECL (LVPECL) clock signals (CPU_CLK, UPA_CLK0 and UPA_CLK1) from the systemboard and terminates them. The CPU_CLK is unique in the system, but the UPA_CLKs are two of many UPA clock inputs in the system. The CPU_CLK operates at 1/2 the CPU core frequency. The UPA_CLKs operate at the UPA bus frequency. The CPU to UPA clo
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™ UltraSPARC -II CPU Module SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache . Module Boundary CPU_CLK Module Connector SRAM Serial SRAM Parallel SRAM UDB-II SRAM UPA_CLK0 SRAM Clock Buffer SRAM UDB-II SRAM Clock SRAM Clock Generator Divider SRAM/TAG UltraSPARC-II UPA_CLK1 CPU UPA_CLK Clock Buffer UPA_CLK2 UPA Device UPA_CLKx UPA Device Figure 3. Clock Signal Distribution LOW VOLTAGE PECL Two trace signals compose each clock: one positive signal and one negative signal. Each signal is 180-degrees out
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™ UltraSPARC -II CPU Module Advanced Version 400 MHz CPU, 4.0 MB E-Cache SME5224AUPA-400 ELECTRICAL CHARACTERISTICS [1] Absolute Maximum Ratings Symbol Parameter Rating Units V Supply voltage range for I/O 0 to 3.8 V DD [2] V Supply voltage range for CPU core 0 to 3.0 V DD_CORE [3] V Input voltage range -0.5 to V + 0.5 V I DD V Output voltage range -0.5 to V + 0.5 V O DD I Input clamp current ± 20 mA IK I Output clamp current ± 50 mA OK I Current into any output in the low state 50 mA OL T St
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™ UltraSPARC -II CPU Module SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache [1] DC Characteristics Symbol Parameter Conditions Min Typ Max Units V High-level output voltage V = Min, I = Max 2.4 – – V OH DD OH V High-level input voltage, PECL clocks, 2.28 – – V IH High-level input voltage, 2.0 – – V except PECL clocks V Low-level input voltage, PECL clocks – – 1.49 V IL Low-level input voltage, – – 0.8 V except PECL clocks Low-level output voltage V = Min, I = Max – – 0.4 V V OL DD OL [2] [3] I Sup
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0.5 nH 2 nH 50 Ω 0.5 nH 2 nH 50 Ω ™ UltraSPARC -II CPU Module Advanced Version 400 MHz CPU, 4.0 MB E-Cache SME5224AUPA-400 UPA Data Bus SPICE Model A typical circuit for the UPA data bus and ECC signals is illustrated in Figure 4:. Edge Connector UDB-II Driver 3.1 nH Trace 1 Trace 2 1.0 pF 1.0 pF Edge Connector via 0.6 pF 3.1 nH Trace 3 Trace 4 1.0 pF 1.0 pF via 0.6 pF 7 pF Measure point for XB1 XB1 BGA Package Loading 7 pF Measure point for CPU UDB-II of Second Module Package Loading Worst Case
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™ UltraSPARC -II CPU Module SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UPAACTIMING SPECIFICATIONS The UPA AC Timing Specifications are referenced to the UPA connector. The timing assumes that the clocks are correctly distributed, (see the section "System Clock Distribution," on page 9). The effective PCB clock trace lengths (CPU_CLK, UPA_CLK0 and UPA_CLK1) are used to calculate a balanced clock system. UPA_CLK Module Clocks All the UPA_CLKx trace pairs are the same length coming from the clock b
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™ UltraSPARC -II CPU Module Advanced Version 400 MHz CPU, 4.0 MB E-Cache SME5224AUPA-400 Setup and Hold Time Specifications 400 MHz CPU 100 MHz UPA Symbol Setup Signals and Hold Time Signals Waveforms Min Max Unit t UPA_DATA [127:0] 1 0.4 – ns H Hold time UPA_ADDR [35:0] 1 0.4 – ns UPA_ADDR_VALID, UPA_REQ_IN [2:0], UPA_SC_REQ_IN, UPA_DATA_STALL, UPA_ECC_VALID, UPA_RESET_L, UPA_XIR_L UPA_ECC [15:0] 1 0.4 – ns UPA_S_REPLY [3:0] 1 0.4 – ns The following table, "Propagation Delay, Output Hold Time Sp
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™ UltraSPARC -II CPU Module SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache MECHANICAL SPECIFICATIONS The module components and dimensions are specified in Figure 6, Figure 7, Figure 8 and Figure 9. Module Ejectors CPU/Voltage Regulator Heat Sink Thermistor Location (RT0201) UDB Heat Sinks Front SRAM Heat Sinks Figure 6. CPU Module Components 6.250 [158.75] 0.315 5.890 [149.61] [8.00] 0.179 [4.55] 3.680 4.250 [93.47] [107.95] Pin 328 0.570 [14.48] Pin 1 0.535 [13.59] 0.540 [13.72] 0.112 [2.86 ]
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™ UltraSPARC -II CPU Module Advanced Version 400 MHz CPU, 4.0 MB E-Cache SME5224AUPA-400 Module Shroud Bidirectional Airflow Bidirectional Airflow Backside SRAM Heat sink Figure 8. CPU Module Side View Provide Minimum Frontside Clearance 0.079 [2.00] 1.318 Maximum Card Guide Depth [33.48] 0.087 [2.201] Maximum 0.062 + 0.008 0.298 [1.57 + 0.20] [7.57] Maximum Provide Minimum 0.079 [2.00] Backside Clearance Dimensions: inches [millimeters] Figure 9. CPU Module
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™ UltraSPARC -II CPU Module SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache THERMAL SPECIFICATIONS The maximum CPU operating frequency and I/O timing is reduced when the junction temperature (Tj) of the CPU device is raised. Airflow must be directed to the CPU heatsink to keep the CPU device cool. Correct air- flow maintains the junction temperature within its operating range. The airflow directed to the CPU is usually sufficient to keep the surrounding devices on the topside of the module cool, includi
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™ UltraSPARC -II CPU Module Advanced Version 400 MHz CPU, 4.0 MB E-Cache SME5224AUPA-400 Thermal Definitions and Specifications Term Definition Specification Comments Tj Maximum device 85 °C, The Tj can't be measured directly by a thermo-couple junction probe. It must always be estimated as Tj or less. Less is temperature preferred. Tc Maximum case 76.7 °C Measurable at the top-center of the device. Requires a hole temperature in the base of the heatsink to allow the thermocouple to be in contact w
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™ UltraSPARC -II CPU Module SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache Temperature Estimating and Measuring Methods The following methods can be used to estimate air cooling requirements and calculate junction temperature based on thermo-couple temperature measurements. Airflow Cooling Measurement Method The relationship between air temperature and junction temperature is described in the following thermal equation: Tj = Ta + [Pd (θjc + θcs + θsa)] Note: Testing is done with the worst-case po
