Résumé du contenu de la page N° 1
TMS320C6452 DSP
DDR2 Memory Controller
User's Guide
Literature Number: SPRUF85
October 2007
Résumé du contenu de la page N° 2
2 SPRUF85–October 2007 Submit Documentation Feedback
Résumé du contenu de la page N° 3
Contents Preface ............................................................................................................................... 6 1 Introduction................................................................................................................ 9 1.1 Purpose of the Peripheral....................................................................................... 9 1.2 Features.............................................................................................
Résumé du contenu de la page N° 4
List of Figures 1 DDR2 Memory Controller Block Diagram............................................................................... 10 2 DDR2 Memory Controller Signals........................................................................................ 12 3 DDR2 MRS and EMRS Command ...................................................................................... 14 4 Refresh Command .......................................................................................................
Résumé du contenu de la page N° 5
List of Tables 1 DDR2 Memory Controller Signal Descriptions ......................................................................... 12 2 DDR2 SDRAM Commands ............................................................................................... 13 3 Truth Table for DDR2 SDRAM Commands ............................................................................ 13 4 Addressable Memory Ranges ............................................................................................ 18
Résumé du contenu de la page N° 6
Preface SPRUF85–October 2007 Read This First About This Manual This document describes the operation of the DDR2 Memory Controller in the TMS320C6452. Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown in figures and described in tables. – Each register figure shows a rectangle divided into fields that represent the fie
Résumé du contenu de la page N° 7
www.ti.com Related Documents From Texas Instruments SPRUF87 —TMS320C6452 DSP Host Port Interface (UHPI) User's Guide describes the host port interface (HPI) in the TMS320C6452 Digital Signal Processor (DSP). The HPI is a parallel port through which a host processor can directly access the CPU memory space. The host device functions as a master to the interface, which increases ease of access. The host and CPU can exchange information via internal or external memory. The host also has direct acce
Résumé du contenu de la page N° 8
www.ti.com Related Documents From Texas Instruments SPRUF97 —TMS320C6452 DSP 3 Port Switch (3PSW) Ethernet Subsystem User's Guide describes the operation of the 3 port switch (3PSW) ethernet subsystem in the TMS320C6452 Digital Signal Processor (DSP). The 3 port switch gigabit ethernet subsystem provides ethernet packet communication and can be configured as an ethernet switch. It provides the serial gigabit media independent interface (SGMII), the management data input output (MDIO) for physica
Résumé du contenu de la page N° 9
User's Guide SPRUF85–October 2007 DSP DDR2 Memory Controller 1 Introduction This document describes the DDR2 memory controller in the device. 1.1 Purpose of the Peripheral The DDR2 memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM devices. Memory types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories are not supported. The DDR2 memory controller SDRAM can be used for program and data storage. 1.2 Features The DDR2 memory controller supports the
Résumé du contenu de la page N° 10
www.ti.com Introduction Figure 1. DDR2 Memory Controller Block Diagram L1P cache/SRAM EMIFA L2 memory L1 program memory controller Advanced controller event Cache control triggering Bandwidth management Cache (AET) DDR2 memory control Memory protection controller Bandwidth management C64x+ CPU Memory Instruction fetch PLL2 IDMA protection SPLOOP buffer 16/32−bit instruction dispatch Instruction decode Data path A Data path B External memory L1 S1 M1 D1 D2 M2 S2 L2 controller Configuration Regist
Résumé du contenu de la page N° 11
www.ti.com Peripheral Architecture 2 Peripheral Architecture The DDR2 memory controller can gluelessly interface to most standard DDR2 SDRAM devices and supports such features as self-refresh mode and prioritized refresh. In addition, it provides flexibility through programmable parameters such as the refresh rate, CAS latency, and many SDRAM timing parameters. The following sections describe the architecture of the DDR2 memory controller as well as how to interface and configure it to perform r
Résumé du contenu de la page N° 12
www.ti.com Peripheral Architecture Figure 2. DDR2 Memory Controller Signals DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_WE DDR_RAS DDR2 DDR_CAS memory DDR_DQM[3:0] controller DDR_DQS[3:0] DDR_DQS[3:0] DDR_BA[2:0] DDR_A[13:0] DDR_D[31:0] DDR_ODT[1:0] DDR_DQGATE[3:0] DDR_VREF Table 1. DDR2 Memory Controller Signal Descriptions Pin Description DDR_D[31:0] Bidirectional data bus. Input for data reads and output for data writes. DDR_A[13:0] External address output. DDR_CS Active-low chip enable for memory spa
Résumé du contenu de la page N° 13
www.ti.com Peripheral Architecture 2.4 Protocol Description(s) The DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 2. Table 3 shows the signal truth table for the DDR2 SDRAM commands. Table 2. DDR2 SDRAM Commands Command Function ACTV Activates the selected bank and row. DCAB Precharge all command. Deactivates (precharges) all banks. DEAC Precharge single command. Deactivates (precharges) a single bank. DESEL Device Deselect. EMRS Extended Mode Register set. Allows alteri
Résumé du contenu de la page N° 14
www.ti.com Peripheral Architecture 2.4.1 Mode Register Set (MRS and EMRS) DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory for operation. These registers control burst type, burst length, CAS latency, DLL enable/disable, single-ended strobe, etc. The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by issuing MRS and EMRS commands. When the MRS or EMRS command is executed, the value on DDR_BA[1:0] selects the mode register
Résumé du contenu de la page N° 15
www.ti.com Peripheral Architecture Figure 4. Refresh Command REFR DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_A[13:0] DDR_BA[2:0] DDR_DQM[3:0] 2.4.3 Activation (ACTV) The DDR2 memory controller automatically issues the activate (ACTV) command before a read or write to a closed row of memory. The ACTV command opens a row of memory, allowing future accesses (reads or writes) with minimum latency. The value of DDR_BA[2:0] selects the bank and the value of A[12:0] selects the row. When
Résumé du contenu de la page N° 16
www.ti.com Peripheral Architecture 2.4.4 Deactivation (DCAB and DEAC) The precharge all banks command (DCAB) is performed after a reset to the DDR2 memory controller or following the initialization sequence. DDR2 SDRAMs also require this cycle prior to a refresh (REFR) and mode set register commands (MRS and EMRS). During a DCAB command, DDR_A[10] is driven high to ensure the deactivation of all banks. Figure 6 shows the timing diagram for a DCAB command. Figure 6. DCAB Command DCAB DDR_CLK DDR_
Résumé du contenu de la page N° 17
www.ti.com Peripheral Architecture 2.4.5 READ Command Figure 8 shows the DDR2 memory controller performing a read burst from DDR2 SDRAM. The READ command initiates a burst read operation to an active row. During the READ command, DDR_CAS drives low, DDR_WE and DDR_RAS remain high, the column address is driven on DDR_A[12:0], and the bank address is driven on DDR_BA[2:0]. The DDR2 memory controller uses a burst length of 8, and has a programmable CAS latency of 2, 3, 4, or 5. The CAS latency is t
Résumé du contenu de la page N° 18
www.ti.com Peripheral Architecture 2.4.6 Write (WRT) Command Prior to a WRT command, the desired bank and row are activated by the ACTV command. Following the WRT command, a write latency is incurred. Write latency is equal to CAS latency minus 1. All writes have a burst length of 8. The use of the DDR_DQM outputs allows byte and halfword writes to be executed. Figure 9 shows the timing for a write on the DDR2 memory controller. If the transfer request is for less than 8 words, depending on the
Résumé du contenu de la page N° 19
www.ti.com Peripheral Architecture Figure 10 shows the byte lanes used on the DDR2 memory controller. The external memory is always right aligned on the data bus. Figure 10. Byte Alignment DDR2 memory controller data bus DDR_D[23:16] DDR_D[31:24] DDR_D[15:8] DDR_D[7:0] (Byte Lane 2) (Byte Lane 3) (Byte Lane 1) (Byte Lane 0) 32-bit memory device 16-bit memory device 2.6 Address Mapping The DDR2 memory controller views external DDR2 SDRAM as one continuous block of memory. This statement is true r
Résumé du contenu de la page N° 20
www.ti.com Peripheral Architecture SDCFG Bit Logical Address IBANK PAGESIZE 31:28 27 26 25 24 23 22:17 16 15 14 13 12 11 10 9:2 (1) 0 0 X X X X X nrb=14 ncb=8 1 0 X X X X nrb=14 nbb=1 ncb=8 2 0 X X X nrb=14 nbb=2 ncb=8 3 0 X X nrb=14 nbb=3 ncb=8 0 1 X X X X nrb=14 ncb=9 1 1 X X X nrb=14 nbb=1 ncb=9 2 1 X X nrb=14 nbb=2 ncb=9 3 1 X nrb=14 nbb=3 ncb=9 0 2 X X X nrb=14 ncb=10 1 2 X X nrb=14 nbb=1 ncb=10 2 2 X nrb=14 nbb=2 ncb=10 3 2 X nrb=13 nbb=3 ncb=10 0 3 X X nrb=14 ncb=11 1 3 X nrb=14 nbb=1 ncb
