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S1D13504 Color Graphics LCD/CRT Controller
S1D13504
TECHNICAL MANUAL
Document Number: X19A-Q-002-14
Copyright © 1997, 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurat
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Epson Research and Development Page 3 Vancouver Design Center Customer Support Information Comprehensive Support Tools Seiko Epson Corp. provides to the system designer and computer OEM manufacturer a complete set of resources and tools for the development of graphics systems. Evaluation / Demonstration Board • Assembled and fully tested graphics evaluation board with installation guide and schematics. To borrow an evaluation board, please contact your local Seiko Epson Corp. sales representa
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ENERGY SAVING EPSON GRAPHICS S1D13504 S1D13504 COLOR GRAPHICS LCD/CRT CONTROLLER February 2001 DESCRIPTION The S1D13504 is a low cost, low power, color/monochrome LCD/CRT controller interfacing to a wide range of CPUs and LCDs. The S1D13504 architecture is designed to meet the requirements of embedded markets such as Office Automation equipment, Mobile Communications devices and Hand-Held PCs where Windows CE may serve as a primary operating system. The S1D13504 supports LCD interfaces wi
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GRAPHICS S1D13504 SYSTEM BLOCK DIAGRAM RAMDAC EDO-DRAM Analog Out FPM-DRAM CRT Control Digital Out CPU Clock S1D13504 Flat Panel FOR SYSTEM INTEGRATION SERVICES CONTACT YOUR SALES REPRESENTATIVE FOR THESE FOR WINDOWS® CE CONTACT: COMPREHENSIVE DESIGN TOOLS: Epson Research & Development, Inc. S1D13504 Technical Manual Suite #320 - 11120 Horseshoe Way Richmond, B.C., Canada V7A 5H7 S5U13504 Evaluation Boards Tel: (604) 275-5151 Fax: (604) 275-2167 Windows CE Display Driver Email: wince@e
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S1D13504 Color Graphics LCD/CRT Controller Hardware Functional Specification Document Number: X19A-A-002-18 Copyright © 1997, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are
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Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 Overview Description . . . . . . . . . . . . . . . . . . . .
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Page 4 Epson Research and Development Vancouver Design Center 7.1.2 MC68K Bus 1 Interface Timing (e.g. MC68000) . . . . . . . . . . . . . . . . . . . . . . . .38 7.1.3 MC68K Bus 2 Interface Timing (e.g. MC68030) . . . . . . . . . . . . . . . . . . . . . . . .40 7.1.4 Generic MPU Interface Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . .42 7.1.5 Generic MPU Interface Asynchronous Timing . . . . .
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Epson Research and Development Page 5 Vancouver Design Center 8.2.9 External RAMDAC Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9 Display Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.1 Image Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 9
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Epson Research and Development Page 7 Vancouver Design Center List of Tables Table 2-1: S1D13504 Series Package list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 5-1: Host Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 5-2: Memory Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .
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Page 8 Epson Research and Development Vancouver Design Center Table 7-25: Dual Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Table 7-26: Dual Color 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Table 7-27: Dual Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Ta
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Epson Research and Development Page 9 Vancouver Design Center List of Figures Figure 3-1: Typical System Diagram – SH-3 Bus, 1Mx16 FPM/EDO-DRAM . . . . . . . . . . . . . . . . . 14 Figure 3-2: Typical System Diagram – MC68K Bus 1, 1Mx16 FPM/EDO-DRAM (16-Bit MC68000) . . . . 15 Figure 3-3: Typical System Diagram – MC68K Bus 2, 256Kx16 FPM/EDO-DRAM (32-Bit MC68030) . . 15 Figure 3-4: Typical System Diagram – Generic Bus, 1Mx16 FPM/EDO-DRAM . . . . . . . . . . . .
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Page 10 Epson Research and Development Vancouver Design Center Figure 7-33: Dual Color 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 7-34: Dual Color 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 7-35: Dual Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Epson Research and Development Page 11 Vancouver Design Center 1 Introduction 1.1 Scope This is the Functional Specification for the S1D13504 Series Color Graphics LCD/CRT Controller Chip. Included in this document are timing diagrams, AC and DC characteristics, register descrip- tions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers. 1.2 Overview Description The S1D13504 is a low cost, low power color/monochr
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Page 12 Epson Research and Development Vancouver Design Center 2 Features 2.1 Memory Interface 16-bit DRAM interface: EDO-DRAM up to 40MHz data rate (80M bytes per second). FPM-DRAM up to 25MHz data rate (50M bytes per second). Memory size options: 512K bytes using one 256K ×16 device. 2M bytes using one 1M ×16 device. A configuration register can be programmed to enhance performance by tailoring the memory control output timing to the DRAM device. 2.2 CPU Interface Supports
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Epson Research and Development Page 13 Vancouver Design Center 2.4 Display Modes 1/2/4/8/16 bit-per-pixel modes supported on LCD. 1/2/4/8 bit-per-pixel modes supported on CRT. Up to 16 shades of gray by FRM on monochrome passive LCD panels; a 16x4 Look-Up Table is used to map 1/2/4 bit-per-pixel modes into these shades. Up to 4096 colors on color passive LCD panels; three 16x4 Look-Up Tables are used to map 1/2/4/8 bit-per-pixel modes into these colors, 16 bit-per-pixel mode is mapped
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Page 14 Epson Research and Development Vancouver Design Center 3 Typical System Implementation Diagrams Power Oscillator Management SH-3 BUS M/R# A21 CSn# CS# A[20:0] AB[20:0] FPDAT[15:8] UD[7:0] D[15:0] DB[15:0] FPDAT[7:0] LD[7:0] 4/8/16-bit FPSHIFT FPSHIFT WE1# WE1# LCD BS# BS# S1D13504 FPFRAME FPFRAME Display RD/WR# RD/WR# FPLINE FPLINE RD# RD# DRDY MOD WE0# WE0# WAIT# WAIT# LCDPWR CKIO BUSCLK RESET# RESET# 1Mx16 FPM/EDO-DRAM Figure 3-1: Typical System Diagram – SH-3 Bus, 1Mx16 FPM/EDO-DRAM
