Résumé du contenu de la page N° 1
CY25822-2
CK-SSC Spread Spectrum Clock Generator
Features
• 3.3V operation
48- and 66-MHz frequency support
Selectable slew rate control
350-pS jitter
2
I C programmability
500- µ A power-down current
Spread Spectrum for best electromagnetic interference
(EMI) reduction
8-pin SOIC package
Block Diagram
VDD
REFOUT
CLKOUT
Clock Input
Freq. Phase Charge Post
(SSCG Output)
VCO
Σ
Divider Detector Pump Dividers
M
Modulating
SDATA
Waveform
Logic
SCLOCK
Feedback
Control
PWRDWN# Divider
N
Résumé du contenu de la page N° 2
CY25822-2 Pin Description Pin No. Pin Name Pin Type Pin Description 1 CLKIN Input 48-MHz or 66-MHz Clock Input. 2 VDD Power Power Supply for PLL and Outputs. 3 GND Ground Ground for Outputs. 4 CLKOUT Output 48-MHz or 66-MHz Spread Spectrum Clock Output. 5REFOUT Output Non-spread Spectrum Reference Clock Output. 2 6 SDATA I/O I C-compatible SDATA. 2 7 SCLOCK Input I C-compatible SCLOCK. 8 PWRDWN# Output LVTTL Input for PowerDown# Active Low. Serial Data Interface Data Protocol To enhance the flex
Résumé du contenu de la page N° 3
CY25822-2 Table 2. Block Read and Block Write Protocol (continued) .... Data Byte N –8 bits 56 Acknowledge .... Acknowledge from slave .... Data bytes from slave/Acknowledge .... Stop .... Data byte N from slave – 8 bits .... Not Acknowledge .... Stop Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Byte Read Protocol Bit Description Bit Description 1Start 1Start 2:8 Slave address – 7 bits 2:8 Slave address – 7 bits 9 Write = 0 9 Write = 0 10 Acknowledge from slave 10 Acknowl
Résumé du contenu de la page N° 4
CY25822-2 Table 4. Spread Spectrum Select (continued) SS3 SS2 SS1 SS0 Spread Mode Spread Amount% 0 1 0 1 Down 2.0 0 1 1 0 Down 2.5 0 1 1 1 Down 3.0 10 0 0 Center ±0.3 10 0 1 Center ±0.4 10 1 0 Center ±0.5 10 1 1 Center ±0.6 11 0 0 Center ±0.8 11 0 1 Center ±1.0 11 1 0 Center ±1.25 11 1 1 Center ±1.5 Byte 1: Control Register Bit @Pup Pin# Name Pin Description 7 1 5 REFEN REFOUT enable 0 = disabled, 1 = enabled 6 1 5 REFSLEW REFOUT edge rate control 0 = slow, 1 = nominal 5 0 Not Applicable Reserv
Résumé du contenu de la page N° 5
CY25822-2 PWRDWN# CLKOUT REFOUT Figure 1. Power-down Assertion PD# <3.0ms CLKOUT REFOUT Figure 2. Power-down Deassertion CLKOUT and REFOUT Enable Clarification 2 The CLKOUT enable and REFOUT enable I C register bits are used to shot-off the CLKOUT and REFOUT clocks individually. The VCO and crystal oscillator must remain on. A shutdown clock is driven low. ALL clocks need to be stopped in a predictable manner. All clocks need to be shutdown without any glitches or other abnormal behavior while
Résumé du contenu de la page N° 6
CY25822-2 Table 5. Absolute Maximum Ratings Parameter Description Condition Min. Max. Unit V Core Supply Voltage –0.5 4.6 V DD V Analog Supply Voltage –0.5 4.6 V DD_A V Input Voltage Relative to V –0.5 V + 0.5 VDC IN SS DD T Temperature, Storage Non Functional –65 +150 °C S T Temperature, Operating Ambient Functional 0 70 °C A T Temperature, Junction Functional – 150 °C J ESD ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – Volts HBM UL–94 Flammability Rating @1/8 in. V–0
Résumé du contenu de la page N° 7
CY25822-2 Table 7. AC Parameters (T = 0°C to +70°C, V = 3.3V ± 5%) (continued) A DD Parameter Description Conditions Min. Max. Unit Notes t Falling Edge Rate Measured from 2.4V to 0.4V 1.33 4.0 V/ns Low Buffer Strength FALLL1 2 REFOUT and CLOCKOUT Refer to I C Control t Rise Time Measured from 0.4V to 2.4V 0.4 1.0 ns High Buffer Strength RISEH2 2 REFOUT and CLOCKOUT Refer to I C Control t Fall Time Measured from 2.4V to 0.4V 0.4 1.0 ns High Buffer Strength FALLH2 2 REFOUT and CLOCKOUT Refer to
Résumé du contenu de la page N° 8
CY25822-2 Package Diagram 8-lead (150-Mil) SOIC – S8 51-85066-*B 2 Purchase of I C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips 2 2 2 I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips.All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-07531 Rev. ** Page 8 of 9 © Cypr
Résumé du contenu de la page N° 9
CY25822-2 Document History Page Document Title: CY25822-2 CK-SSC Spread Spectrum Clock Generator Document Number: 38-07531 Issue Orig. of REV. ECN NO. Date Change Description of Change ** 124462 03/19/03 RGL New Data Sheet Document #: 38-07531 Rev. ** Page 9 of 9 [+] Feedback
