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CY7C1371D
CY7C1373D
18-Mbit (512K x 36/1M x 18)
Flow-Through SRAM with NoBL™ Architecture
[1]
Features Functional Description
• No Bus Latency™ (NoBL™) architecture eliminates dead The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1M x 18
cycles between write and read cycles Synchronous flow through Burst SRAM designed specifically
to support unlimited true back-to-back Read/Write operations
• Supports up to 133-MHz bus operations with zero wait
with no wait state insertion. The CY7C1371D/CY7C1373D
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CY7C1371D CY7C1373D Logic Block Diagram – CY7C1371D (512K x 36) ADDRESS A0, A1, A REGISTER A1 A1' D1 Q1 A0 A0' D0 Q0 MODE BURST CE ADV/LD CLK C LOGIC C CEN WRITE ADDRESS REGISTER O U T P D S U A E T T ADV/LD N A S B MEMORY BW A WRITE E U WRITE REGISTRY S ARRAY DQs DRIVERS F BW B AND DATA COHERENCY T DQP A A F E CONTROL LOGIC DQP B BW C M E E DQP C P R R BW D DQP D S S I WE N E G INPUT E REGISTER OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Logic Block Diagram – CY7C1373D (1M x 18) ADDRESS A0, A1
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CY7C1371D CY7C1373D Pin Configurations 100-Pin TQFP Pinout DQP 80 C 1 DQP B DQ 79 2 C DQ B DQ 78 C 3 DQ B V 77 4 DDQ V DDQ V 76 5 V SS SS DQ 75 6 DQ C B BYTE C BYTE B DQ 74 C 7 DQ B DQ 73 8 C DQ B DQ 72 C 9 DQ B V 71 10 SS V SS V 70 DDQ 11 V DDQ DQ 69 12 DQ C B DQ 68 C 13 DQ B CY7C1371D NC 67 14 V SS V 66 15 DD NC NC 65 16 V DD V 64 17 ZZ SS DQ 63 18 DQ D A DQ 62 19 D DQ A V 61 20 V DDQ DDQ V 60 21 SS V SS DQ 59 22 DQ D A DQ 58 23 D DQ BYTE D A BYTE A DQ 57 24 DQ D A DQ 56 25 D DQ A V 55 26
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CY7C1371D CY7C1373D Pin Configurations (continued) 100-Pin TQFP Pinout NC 80 1 A NC 79 2 NC NC 78 3 NC V 77 4 DDQ V DDQ V 76 5 V SS SS NC 75 6 NC NC 74 7 DQP A DQ 73 8 B DQ A DQ 72 B 9 DQ A V 71 10 SS V SS V 70 DDQ 11 V DDQ DQ 69 12 DQ B A DQ 68 B 13 DQ A CY7C1373D NC 67 14 V SS BYTE A V 66 15 DD NC BYTE B NC 65 16 V DD V 64 17 ZZ SS DQ 63 18 DQ B A DQ 62 19 B DQ A V 61 20 V DDQ DDQ V 60 21 SS V SS DQ 59 22 DQ B A DQ 58 23 B DQ A DQP 57 24 NC B NC 56 25 NC V 55 26 V SS SS V 54 27 DDQ V DDQ
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CY7C1371D CY7C1373D Pin Configurations (continued) 119-Ball BGA Pinout CY7C1371D (512K x 36) 1 23 4 5 6 7 A A V AA A A V DDQ DDQ B NC/576M CE A ADV/LD A CE NC 2 3 C NC/1G A A V A A NC DD D DQ DQP V NC V DQP DQ C C SS SS B B E DQ DQ V V DQ DQ CE C C SS SS B B 1 F V DQ V V DQ V OE DDQ C SS SS B DDQ G DQ DQ A DQ DQ BW BW C C B B C B H DQ DQ V V DQ DQ WE C C SS SS B B J V V NC V NC V V DDQ DD DD DD DDQ K DQ DQ V CLK V DQ DQ D D SS SS A A L DQ DQ BW NC BW DQ DQ D D A A D A M V DQ V V DQ V CEN DDQ
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CY7C1371D CY7C1373D Pin Configurations (continued) 165-Ball FBGA Pinout CY7C1371D (512K x 36) 1 23 4 5 6 7 89 10 11 A A NC/576M CE BW BW CE CEN ADV/LD A NC A 1 C B 3 B NC/1G A CE2 BW BW CLK WE OE A A NC D A DQP NC V V V V V V V NC DQP C C DDQ SS SS SS SS SS DDQ B D DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B E DQ DQ V V V V V V V DQ DQ C C DDQ DD SS SS SS DD DDQ B B DQ DQ V V V V V V V DQ DQ F C DD SS DD B C DDQ SS SS DDQ B DQ DQ V V V V V V V DQ DQ G C C DDQ DD SS SS SS DD DDQ
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CY7C1371D CY7C1373D Pin Definitions Name IO Description A , A , A Input- Address Inputs used to select one of the address locations. Sampled at the rising edge of the 0 1 Synchronous CLK. A are fed to the two-bit burst counter. [1:0] Input- Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on BW , BW A B Synchronous the rising edge of CLK. BW , BW C D WE Input- Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
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CY7C1371D CY7C1373D Pin Definitions (continued) Name IO Description TDO JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG output feature is not being used, this pin must be left unconnected. This pin is not available on TQFP Synchronous packages. TDI JTAG serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not input being used, this pin can be left floating or connected to V through a pull
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CY7C1371D CY7C1373D details) inputs is latched into the device and the write is clock cycles are required to enter into or exit from this “sleep” complete. Additional accesses (Read/Write/Deselect) can be mode. While in this mode, data integrity is guaranteed. initiated on this cycle. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation The data written during the Write operation is controlled by guaranteed. The device must be deselect
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CY7C1371D CY7C1373D [2, 3, 4, 5, 6, 7, 8] Truth Table Address Operation Used CE CE ZZ ADV/LD WE BW OE CEN CLK DQ CE 1 2 X 3 Deselect Cycle None H X X L L X X X L L->H Tri-State Deselect Cycle None X X H L L X X X L L->H Tri-State Deselect Cycle None X L X L L X X X L L->H Tri-State Continue Deselect Cycle None X X X L H X X X L L->H Tri-State Read Cycle (Begin Burst) External L H L L L H X L L L->H Data Out (Q) Read Cycle (Continue Burst) Next X X X L H X X L L L->H Data Out (Q) NOP/Dummy Rea
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CY7C1371D CY7C1373D Test Data-In (TDI) IEEE 1149.1 Serial Boundary Scan (JTAG) The TDI ball is used to serially input information into the The CY7C1371D/CY7C1373D incorporates a serial boundary registers and can be connected to the input of any of the scan test access port (TAP).This part is fully compliant with registers. The register between TDI and TDO is chosen by the 1149.1. The TAP operates using JEDEC-standard 3.3V or instruction that is loaded into the TAP instruction register. For 2.5
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CY7C1371D CY7C1373D instruction if the controller is placed in a reset state as access between the TDI and TDO in the shift-DR controller described in the previous section. state. When the TAP controller is in the Capture-IR state, the two IDCODE least significant bits are loaded with a binary “01” pattern to The IDCODE instruction causes a vendor-specific, 32-bit code allow for fault isolation of the board level serial test data path. to be loaded into the instruction register. It also place
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CY7C1371D CY7C1373D boundary scan path when multiple devices are connected This bit can be set by entering the SAMPLE/PRELOAD or together on a board. EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR,” the value EXTEST Output Bus Tri-State loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit IEEE Standard 1149.1 mandates that the TAP controller be directly controls
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CY7C1371D CY7C1373D [10, 11] TAP AC Switching Characteristics Over the Operating Range Parameter Description Min Max Unit Clock t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH time 20 ns TH t TCK Clock LOW time 20 ns TL Output Times t TCK Clock LOW to TDO Valid 10 ns TDOV t TCK Clock LOW to TDO Invalid 0 ns TDOX Setup Times t TMS Setup to TCK Clock Rise 5 ns TMSS t TDI Setup to TCK Clock Rise 5 ns TDIS t Capture Setup to TCK Rise 5 ns CS Hold Times t TMS Hold
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CY7C1371D CY7C1373D 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ............................................... .V to 3.3V Input pulse level...................................................V to 2.5V SS SS Input rise and fall times................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels...........................................1.5V Input timing refer
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CY7C1371D CY7C1373D Identification Register Definitions CY7C1371D CY7C1373D Instruction Field (512K X 36) (1M X 18) Description Revision Number (31:29) 000 000 Describes the version number Device Depth (28:24) 01011 01011 Reserved for internal use Device Width (23:18) 001001 001001 Defines memory type and architecture Cypress Device ID (17:12) 100101 010101 Defines width and density Cypress JEDEC ID Code (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor ID Register Pre
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CY7C1371D CY7C1373D [13, 14] 119-Ball BGA Boundary Scan Order Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 23 F6 45 G4 67 L1 H4 2 T4 24E7 46A4 68 M2 3T5 25 D7 47 G3 69 N1 4 T6 26H7 48C3 70 P1 5R5 27 G6 49 B2 71 K1 6 L5 28E6 50B3 72 L2 7 R629 D651 A3 73 N2 8 U630 C752 C274 P2 9 R7 31B7 53A2 75 R3 10 T7 32 C6 54 B1 76 T1 11 P6 33 A6 55 C1 77 R1 12 N7 34 C5 56 D2 78 T2 13 M6 35 B5 57 E1 79 L3 14 L7 36 G5 58 F2 80 R2 15 K6 37 B6 59 G1 81 T3 16 P7 38 D4 60 H2 82 L4 17 N6 39 B4 61 D1 83
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CY7C1371D CY7C1373D [13, 15] 165-Ball BGA Boundary Scan Order Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2N7 32 C11 62 D2 3 N10 33 A11 63 E2 4P11 34 B11 64 F2 5P8 35 A10 65 G2 6R8 36 B10 66 H1 7R9 37 A9 67 H3 8 P938 B968 J1 9 P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11 47 A5 77 N2 18 M10 48 A4 78 P1 19 L10 49 B4 79 R1 20 K10 50 B3 80 R2 21 J10 51 A3 81 P3 22 H9 52 A
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CY7C1371D CY7C1373D DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW)......................................... 20 mA Exceeding maximum ratings may impair the useful life of the Static Discharge Voltage.......................................... > 2001V device. These user guidelines are not tested. (MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch up Current.....................
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CY7C1371D CY7C1373D [18] Capacitance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Package Package Package Unit C Input Capacitance T = 25°C, f = 1 MHz, 589 pF IN A V = 3.3V DD C Clock Input Capacitance 5 8 9 pF CLK V = 2.5V DDQ C Input/Output Capacitance 5 8 9 pF IO [18] Thermal Resistance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Package Package Package Unit Θ Thermal Resistance Test conditions follow standard 28.66 23.8 20.7 °C/W JA (Junction to Ambi
