ページ1に含まれる内容の要旨
Product Preview DS21Q55
PRODUCT PREVIEW
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DS21Q55 Quad T1/E1/J1 Transceiver
FEATURES: APPLICATIONS:
Complete T1 (DS1)/ISDN–PRI/J1 transceiver § Routers
functionality § Channel Service Units (CSUs)
§ Complete E1 (CEPT) PCM-30/ISDN-PRI § Data Service Units (DSUs)
transceiver functionality § Muxes
§ Short- and long-haul line interface for § Switches
clock/data recovery and wave shaping § Channel Banks
§ CMI coder/decoder § T1/E1 Test Equipment
§ Crystal-less jitter attenua
ページ2に含まれる内容の要旨
Product Preview DS21Q55 1. DESCRIPTION The DS21Q55 is a quad MCM devices featuring independent transceivers that can be software configured for T1, E1, or J1 operation. Each is composed of a line interface unit (LIU), framer, HDLC controllers, and a TDM backplane interface, and is controlled via an 8-bit parallel port configured for Intel or Motorola bus operations. The DS21Q55 is software compatible with the DS2155 single transceiver. It is pin compatible with the DS21Qx5y family o
ページ3に含まれる内容の要旨
Product Preview DS21Q55 The device fully meets all of the latest E1 and T1 specifications, including the following: § ANSI: T1.403-1995, T1.231-1993, T1.408 § AT&T: TR54016, TR62411 § ITU: G.703, G.704, G.706, G.736, G.775, G.823, G.932, I.431, O.151, O.161 § ETSI: ETS 300 011, ETS 300 166, ETS 300 233, CTR4, CTR12 § Japanese: JTG.703, JTI.431, JJ-20.11 (CMI coding only) 3 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated
ページ4に含まれる内容の要旨
Product Preview DS21Q55 1.1 FEATURE HIGHLIGHTS The DS21Q55 contains all of the features of the previous generation of Dallas Semiconductor’s T1 and E1 transceivers plus many new features. 1.1.1 General § 27mm, 1.27 pitch BGA § 3.3V supply with 5V tolerant inputs and outputs § Pin compatible with DS21x5y family § Software compatible with the DS2155 § Evaluation kits § IEEE 1149.1 JTAG-boundary scan § Driver source code available from the factory 1.1.2 Line Interface § Requires a
ページ5に含まれる内容の要旨
Product Preview DS21Q55 § Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.544MHz for T1 operation § Can be placed in either the receive or transmit path or disabled § Limit trip indication 1.1.5 Framer/Formatter § Fully independent transmit and receive functionality § Full receive- and transmit-path transparency § T1 framing formats include D4 (SLC-96) and ESF § Detailed alarm- and status-reporting with optional interrupt support § Large
ページ6に含まれる内容の要旨
Product Preview DS21Q55 § Hardware-signaling capability - Receive-signaling reinsertion to a backplane, multiframe sync - Availability of signaling in a separate PCM data stream - Signaling freezing § Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode § Access to the data streams in between the framer/formatter and the elastic stores § User-selectable synthesized clock output 1.1.7 HDLC Controllers § Two independent HDLC controllers § Fa
ページ7に含まれる内容の要旨
Product Preview DS21Q55 Note: This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In each 125μs T1 frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by channel 1. Each channel is made up of 8 bits, which are numbered 1 to 8. Bit 1, the MSB, is transmitted first. Bit 8, the LSB, is transmitted last. The term “locked” is used to refer to two clock signals that are phase- or frequency-locked
ページ8に含まれる内容の要旨
Product Preview DS21Q55 TABLE OF CONTENTS 1.1 FEATURE HIGHLIGHTS ............................................................................................................................4 1.1.1 General ..................................................................................................................................................4 1.1.2 Line Interface........................................................................................................................
ページ9に含まれる内容の要旨
Product Preview DS21Q55 12. LOOPBACK CONFIGURATION .............................................................................................................68 12.1 PER-CHANNEL LOOPBACK...........................................................................................................................70 13. ERROR COUNT REGISTERS .................................................................................................................72 13.1 LINE CODE VIOLATION COUNT REGIST
ページ10に含まれる内容の要旨
Product Preview DS21Q55 22.3.4 Receive Packet Bytes Available ...............................................................................................144 22.3.5 HDLC FIFOS....................................................................................................................................145 22.4 RECEIVE HDLC CODE EXAMPLE............................................................................................................. 146 22.5 LEGACY FDL SUPPORT (T1 MODE)..
ページ11に含まれる内容の要旨
Product Preview DS21Q55 32.2 E1 MODE...................................................................................................................................................... 218 33. OPERATING PARAMETERS .................................................................................................................231 34. AC TIMING PARAMETERS AND DIAGRAMS ...............................................................................233 34.1 MULTIPEXED BUS AC CHARACTERISTICS.
ページ12に含まれる内容の要旨
Product Preview DS21Q55 1.2 DOCUMENT REVISION HISTORY 1) Initial Preliminary Release 12 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
ページ13に含まれる内容の要旨
Transmit Line I/F INT* MUX RD*(DS*) WR*(R/W*) BTS CS1* CS2* CS3* CS4* TSTRST A7/ALE(AS) A6 A5 A4 A3 A2 A1 A0 D7/AD7 D6/AD6 D5/AD5 D4/AD4 D3/AD3 D2/AD2 D1/AD1 D0/AD0 JTCLK Framer Loopback JTDI JTMS Remote Loopback JTTST JTDO RPOSI TPOSO RNEGI TNEGO RCLKI TCLKO Jitter Attenuator TPOSI RPOSO Either transmit or receive path TNEGI RNEGO TCLKI RCLKO Local Loopback LIUCI Receive Line I/F MCLK2 Clock / Data Recovery MCLK1 Product Preview DS21Q55 2. BLOCK DIAGRAM A simplified block diagram showing t
ページ14に含まれる内容の要旨
Product Preview DS21Q55 3. PIN FUNCTION DESCRIPTION 3.1 Transmit Side Pins Signal Name: TCLKx Signal Description: Transmit Clock Signal Type: Input A 1.544 MHz or a 2.048MHz primary clock. Used to clock data through the transmit -side formatter. Signal Name: TSERx Signal Description: Transmit Serial Data Signal Type: Input Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK wh
ページ15に含まれる内容の要旨
Product Preview DS21Q55 Signal Name: TSYNCx Signal Description: Transmit Sync Signal Type: Input/Output A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Can be programmed to output either a frame or multiframe pulse. If this pin is set to output pulses at frame boundaries, it can also be set via IOCR1.3 to output double-wide pulses at signaling frames in T1 mode. Signal Name: TSSYNCx Signal Description: Transmit System Sync Signal T
ページ16に含まれる内容の要旨
Product Preview DS21Q55 Signal Name: TNEGIx Signal Description: Transmit Negative Data Input Signal Type: Input Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TNEGO by tying the LIUC pin high. TPOSI and TNEGI can be tied together in NRZ applications. Signal Name: TCLKIx Signal Description: Transmit Clock Input Signal Type: Input Line interface transmit clock. Can be internally connected to TCLKO by tying the LI
ページ17に含まれる内容の要旨
Product Preview DS21Q55 Signal Name: RSYNCx Signal Description: Receive Sync Signal Type: Input/Output An extracted pulse, one RCLK wide, is output at this pin which identifies either frame (IOCR1.5 = 0) or multiframe (IOCR1.5 = 1) boundaries. If set to output-frame boundaries then via IOCR1.6, RSYNC can also be set to output double-wide pulses on signaling frames in T1 mode. If the receive-side elastic store is enabled, then this pin can be enabled to be an input via IOCR1.4 at whi
ページ18に含まれる内容の要旨
Product Preview DS21Q55 Signal Name: BPCLKx Signal Description: Back Plane Clock Signal Type: Output A user-selectable synthesized clock output that is referenced to the clock that is output at the RCLK pin. Signal Name: RPOSOx Signal Description: Receive Positive Data Output Signal Type: Output Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally tied to RPOSI. Signal Name: RNEGOx Signal Description: Receive Negative Data Ou
ページ19に含まれる内容の要旨
Product Preview DS21Q55 Signal Name: MUX Signal Description: Bus Operation Signal Type: Input Set low to select nonmultiplexed bus operation. Set high to select multiplexed bus operation. Signal Name: D0/AD0 to D7/AD7 Signal Description: Data Bus [D0 to D7] or Address/Data Bus Signal Type: Input/Output In nonmultiplexed bus operation (MUX = 0), it serves as the data bus. In multiplexed bus operation (MUX = 1), it serves as an 8-bit, multiplexed address/data bus. Signal Name: A
ページ20に含まれる内容の要旨
Product Preview DS21Q55 Signal Name: A7/ALE(AS) Signal Description: A7 or Address Latch Enable(Address Strobe) Signal Type: Input In nonmultiplexed bus operation (MUX = 0), it serves as the upper address bit. In multiplexed bus operation (MUX = 1), it serves to demultiplex the bus on a positive-going edge. Signal Name: WR*(R/W*) Signal Description: Write Input(Read/Write) Signal Type: Input WR* is an active-low signal. 3.4 Extended System Information Bus Signal Name: ESIB
