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TM
24888 Rev 3.03 - July 12, 2004 AMD-8151 AGP Tunnel Data Sheet
Cover page
TM TM
AMD-8151 HyperTransport AGP3.0 Graphics Tunnel
Data Sheet
1Overview
TM TM
The AMD-8151 HyperTransport AGP3.0 Graphics Tunnel (referred to as the IC in this document) is a
HyperTransport™ technology (referred to as link in this document) tunnel developed by AMD that provides an
AGP 3.0 compliant (8x transfer rate) bridge.
1.1 Device Features
• HyperTransport technology tunnel with side A • AGP 8x bridge.
and
ページ2に含まれる内容の要旨
TM 24888 Rev 3.03 - July 12, 2004 AMD-8151 AGP Tunnel Data Sheet © 2004 Advanced Micro Devices, Inc. All rights reserved.The contents of this document are provided in connec- tion with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations or warranties with respect to the accuracy or complete- ness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express,
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TM 24888 Rev 3.03 - July 12, 2004 AMD-8151 AGP Tunnel Data Sheet Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Device Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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TM 24888 Rev 3.03 - July 12, 2004 AMD-8151 AGP Tunnel Data Sheet List of Figures Figure 1: System block diagram................................................................................................................... 1 Figure 2: Configuration space. ................................................................................................................... 14 Figure 3: Ball designations...........................................................................................
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TM 24888 Rev 3.03 - July 12, 2004 AMD-8151 AGP Tunnel Data Sheet List of Tables Table 1: IO signal types. ............................................................................................................................. 6 Table 2: Translation from AGP requests to link requests. ........................................................................ 13 Table 3: Configuration spaces.....................................................................................................
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TM 24888 Rev 3.03 - July 12, 2004 AMD-8151 AGP Tunnel Data Sheet 2 Ordering Information AMD-8151 BL C Case Temperature C = Commercial temperature range Package Type BL = Organic Ball Grid Array with lid Family/Core AMD-8151 3 Signal Descriptions 3.1 Terminology See section 5.1.2 for a description of the register naming convention used in this document. See the TM TM AMD-8151 HyperTransport AGP3.0 Graphics Tunnel Design Guide for additional information. Signals with a # suffix are active low
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TM 24888 Rev 3.03 - July 12, 2004 AMD-8151 AGP Tunnel Data Sheet 3.2 Tunnel Link Signals TM The following are signals associated with the HyperTransport links. [B, A] in the signal names below refer to the A and B sides of the tunnel. [P, N] are the positive and negative sides of differential pairs. Pin name and description IO cell Power During After type plane* reset reset LDTCOMP[3:0]. Link compensation pins for both sides of the tunnel. These are Analog VDD- designed to be connected thr
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TM 24888 Rev 3.03 - July 12, 2004 AMD-8151 AGP Tunnel Data Sheet 3.3 AGP Signals In the table below, “Term” indicates the standard AGP 3.0 termination impedance to ground; “PU” indicates a weak pullup resistor; “PD” indicates a weak pulldown resistor. Pin name and description IO cell Power AGP 3.0 AGP 2.0 type plane Signaling Signaling During After During After reset reset reset reset A_ADSTB0_[P, N]. AGP differential strobe for A_AD[15:0] and IO VDD15 Term Term _P: PU _P: PU A_CBE_L[1:0]
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TM 24888 Rev 3.03 - July 12, 2004 AMD-8151 AGP Tunnel Data Sheet Pin name and description IO cell Power AGP 3.0 AGP 2.0 type plane Signaling Signaling During After During After reset reset reset reset A_GNT#. AGP master grant signal. Output VDD15 Term Low PU High A_IRDY#. AGP master ready signal. IO VDD15 Term Term PU PU A_MB8XDET#. This pin is controlled by DevA:0x40[8XDIS]. It Output VDD15 Low Low Low Low is designed to be connected to the AGP connector to indicate support for AGP 3.0 si
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TM 24888 Rev 3.03 - July 12, 2004 AMD-8151 AGP Tunnel Data Sheet 3.4 Test and Miscellaneous Signals Pin name and description IO cell Power During After type plane reset reset CMPOVR. Link automatic compensation override. 0=Link automatic compensation Input VDD33 is enabled. 1=The compensation values stored in DevA:0x[E0, E4, E8] control the compensation circuit. The state of this signal determines the default value for DevA:0x[E0, E4, E8][ACTL and BCTL] at the rising edge of PWROK. FREE[7
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TM 24888 Rev 3.03 - July 12, 2004 AMD-8151 AGP Tunnel Data Sheet 4 Functional Operation 4.1 Overview TM The IC connects to the host through either the side A or side B HyperTransport link interface. The other side of the tunnel may or may not be connected to another device. Host-initiated transactions that do not target the IC or the bridge flow through the tunnel to the downstream device. Transactions claimed by the device are passed to internal registers or to the AGP bridge. See sectio
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TM 24888 Rev 3.03 - July 12, 2004 AMD-8151 AGP Tunnel Data Sheet In summary, Stop Grant broadcasts with SMAF fields specified by DevA:0xF0[ICGSMAF] enable the clock gating window and STPCLK deassertion broadcasts disable the window. If LDTSTOP# is asserted while the clock gating window is enabled, then clock gating occurs. Also, DevA:0xF0[ECGSMAF] may be used in a similar way to disable A_PCLK and the internal clock grids associated with the AGP bridge. The same rules for the clock gating
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TM 24888 Rev 3.03 - July 12, 2004 AMD-8151 AGP Tunnel Data Sheet All AGP transactions are compliant to AGP ordering rules. APG transactions are translated into link transac- tions as follows: AGP transaction Link transaction High priority write WrSized, posted channel, PassPW = 1 High priority read RdSized, PassPW = 1, response PassPW = 1 Low priority write WrSized, posted channel, PassPW = 0 Low priority read RdSized, PassPW = 0, response PassPW = 1 Low priority flush Flush, PassPW = 0 Low p
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TM 24888 Rev 3.03 - July 12, 2004 AMD-8151 AGP Tunnel Data Sheet The first calibration cycle occurs approximately 4 milliseconds after the deassertion of RESET# (whether AGP 2.0 or 3.0 signaling is enabled). 5 Registers 5.1 Register Overview The IC includes several sets of registers accessed through a variety of address spaces. IO address space refers to register addresses that are accessed through x86 IO instructions such as IN and OUT. PCI configuration space is typically accessed by th
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TM 24888 Rev 3.03 - July 12, 2004 AMD-8151 AGP Tunnel Data Sheet The following are configuration spaces: Device Function Mnemonic Registers "A" 0 DevA:0xXX AGP device header; link and AGP capabilities blocks "B" 0 DevB:0xXX PCI-PCI bridge registers for AGP Table 3: Configuration spaces. The IC does not claim configuration-register accesses to unimplemented functions within its devices (they are forwarded to the other side of the tunnel). Accesses to unimplemented register locations within i
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TM 24888 Rev 3.03 - July 12, 2004 AMD-8151 AGP Tunnel Data Sheet AGP Device Status And Command Register DevA:0x04 Default: 0210 0000h Attribute: See below. Bits Description 31 DPE: detected parity error. Read only. This bit is fixed in the low state. 30 SSE: signaled system error. Read; set by hardware; write 1 to clear. 1=A system error was signaled (both links were flooded with sync packets) as a result of a CRC error (see DevA:0x[C8:C4][CRCFEN, CRCERR]). Note: this bit is cleared by PWR
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TM 24888 Rev 3.03 - July 12, 2004 AMD-8151 AGP Tunnel Data Sheet AGP Device Graphic Virtual Memory Aperture Register DevA:0x10 It is expected that the state of this register is copied into the host by software. This register controls no hard- ware in the IC. Default: 0000 0000 0000 0008h Attribute: See below. Bits Description 63:32 APBARHI. Read-write. Aperture base address register high. Note: bits[63:40] are required to be programmed low; setting any of these bits high results in undefin
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TM 24888 Rev 3.03 - July 12, 2004 AMD-8151 AGP Tunnel Data Sheet AGP Miscellaneous Control Register DevA:0x40 Default: 0000 0000h Attribute: See below. Bits Description 31:8 Reserved. 7 Must be low. This bit is required to be low at all times; setting it high results in undefined behavior. 6 Must be low. This bit is required to be low at all times; setting it high results in undefined behavior. 5 Must be low. This bit is required to be low at all times; setting it high results in undefined
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TM 24888 Rev 3.03 - July 12, 2004 AMD-8151 AGP Tunnel Data Sheet AGP PHY Control Register DevA:0x[54, 50] These registers apply to the compensation values of AGP clock-forwarded data and strobe signals as follows: • DevA:0x50: data signals A_AD[31:0], A_CBE_L[3:0], A_DBI[H, L], and A_SBA[7:0]. • DevA:0x54: strobe signals A_ADSTB[1:0]_[P, N] and A_SBSTB_[P, N]. NCTL, NDATA, and NCOMP are related to (1) the falling edge drive strength of the signals as outputs and (2) the impedance of the s
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TM 24888 Rev 3.03 - July 12, 2004 AMD-8151 AGP Tunnel Data Sheet 15:14 PCTL: AGP PHY P (rising edge) compensation control. Read-write. These two bits combine to specify the PHY rising edge compensation value that is applied to AGP signals as follows: PCTL Description 00b Apply PCOMP directly as the compensation value. 01b Apply PDATA directly as the compensation value. 10b Apply the sum of PCOMP and PDATA as the compensation value. If the sum exceeds 1Fh, then 1Fh is applied. 11b Apply
