ページ1に含まれる内容の要旨
DSP56301 User’s Manual
24-Bit Digital Signal Processor
DSP56301UM/AD
Revision 3, March 2001
ページ2に含まれる内容の要旨
OnCE, DigitalDNA, and the DigitalDNA logo are trademarks of Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incident
ページ3に含まれる内容の要旨
1 Overview 2 Signals/Connections Memory Configuration 3 4 Core Configuration 5 Programming the Peripherals Host Interface (HI32) 6 7 Enhanced Synchronous Serial Interface (ESSI) 8 Serial Communications Interface (SCI) Triple Timer Module 9 A Bootstrap Program B Programming Reference
ページ4に含まれる内容の要旨
1 Overview 2 Signals/Connections 3 Memory Configuration 4 Core Configuration 5 Programming the Peripherals 6 Host Interface (HI32) 7 Enhanced Synchronous Serial Interface (ESSI) 8 Serial Communications Interface (SCI) 9 Triple Timer Module A Bootstrap Program B Programming Reference
ページ5に含まれる内容の要旨
Contents Chapter 1 Overview 1.1 Manual Organization ............................................................................................................. 1-1 1.2 Manual Conventions .............................................................................................................. 1-2 1.3 DSP56300 Core Features.......................................................................................................1-4 1.4 DSP56300 Core Functional Blocks ..........................
ページ6に含まれる内容の要旨
2.8 Enhanced Synchronous Serial Interface 0 ........................................................................... 2-22 2.9 Enhanced Synchronous Serial Interface 1 ........................................................................... 2-25 2.10 Serial Communications Interface (SCI)............................................................................... 2-27 2.11 Timers ...............................................................................................................
ページ7に含まれる内容の要旨
4.9 JTAG Identification (ID) Register....................................................................................... 4-35 4.10 JTAG Boundary Scan Register (BSR)................................................................................. 4-35 Chapter 5 Programming the Peripherals 5.1 Peripheral Initialization Steps................................................................................................ 5-1 5.2 Mapping the Control Registers ....................................
ページ8に含まれる内容の要旨
6.7.10 DSP Host Port GPIO Direction Register (DIRH)................................................................ 6-43 6.7.11 DSP Host Port GPIO Data Register (DATH)...................................................................... 6-43 6.8 Host-Side Programming Model ........................................................................................... 6-44 6.8.1 HI32 Control Register (HCTR) ........................................................................................... 6
ページ9に含まれる内容の要旨
7.5.1 ESSI Control Register A (CRA).......................................................................................... 7-14 7.5.2 ESSI Control Register B (CRB) .......................................................................................... 7-18 7.5.3 ESSI Status Register (SSISR).............................................................................................. 7-28 7.5.4 ESSI Receive Shift Register .....................................................................
ページ10に含まれる内容の要旨
Chapter 9 Triple Timer Module 9.1 Overview................................................................................................................................ 9-1 9.1.1 Triple Timer Module Block Diagram.................................................................................... 9-2 9.1.2 Individual Timer Block Diagram........................................................................................... 9-2 9.2 Operation ..................................................
ページ11に含まれる内容の要旨
Figures 1-1 DSP56301 Block Diagram ................................................................................... 1-11 2-1 Signals Identified by Functional Group ................................................................. 2-2 2-2 Host Interface/Port B Detail Signal Diagram......................................................... 2-3 3-1 Default Settings (0, 0, 0)......................................................................................... 3-7 3-2 16-Bit Space With Default
ページ12に含まれる内容の要旨
6-8 DSP PCI Address Register (DPAR)..................................................................... 6-33 6-9 DSP Status Register (DSR) .................................................................................. 6-35 6-10 DSP PCI Status Register (DPSR)......................................................................... 6-38 6-11 DSP Host Port Direction Register (DIRH)........................................................... 6-43 6-12 DSP Host Port GPIO Data Register (DATH).....
ページ13に含まれる内容の要旨
8-4 SCI Clock Control Register (SCCR).................................................................... 8-19 8-5 SCI Baud Rate Generator ..................................................................................... 8-20 8-6 16 x Serial Clock .................................................................................................. 8-21 8-7 SCI Programming Model—Data Registers.......................................................... 8-22 8-8 Port E Control Register (PCRE X:$FFF
ページ14に含まれる内容の要旨
B-9 DMA Control Registers 5–0 (DCR[5–0]) ............................................................B-21 B-10 DSP Control Register (DCTR).............................................................................B-22 B-11 DSP PCI Control Register (DPCR)......................................................................B-23 B-12 DSP PCI Master Control Register (DPMC).........................................................B-24 B-13 DSP PCI Address Register (DPAR)............................
ページ15に含まれる内容の要旨
Tables 1-1 High True/Low True Signal Conventions ................................................................. 1-2 1-2 DSP56301 Switch Memory Configuration.............................................................. 1-10 1-3 DSP56301 Documentation ...................................................................................... 1-14 2-1 DSP56301 Functional Signal Groupings................................................................... 2-1 2-2 Power Inputs .........................
ページ16に含まれる内容の要旨
6-10 DSP Control Register (DCTR) Bit Definitions ....................................................... 6-23 6-11 DSP PCI Control Register (DPCR) Bit Definitions ................................................ 6-27 6-12 DSP PCI Master Control Register (DMPC) Bit Definitions ................................... 6-31 6-13 DSP PCI Address Register (DPAR) Bit Definitions ............................................... 6-33 6-14 DSP Status Register (DSR) Bit Definitions..............................
ページ17に含まれる内容の要旨
Chapter 1 Overview This manual describes the DSP56301 24-bit digital signal processor (DSP), its memory, operating modes, and peripheral modules. The DSP56301 is an implementation of the DSP56300 core with a unique configuration of on-chip memory, cache, and peripherals. Use this manual in conjunction with the DSP56300 Family Manual (DSP56300FM/AD), which describes the CPU, core programming models, and instruction set details. DSP56301 Technical Data (DSP56301/D)—referred to as the data shee
ページ18に含まれる内容の要旨
Manual Conventions n Chapter 6, Host Interface (HI32) HI32 features, signals, architecture, programming model, reset, interrupts, external host programming model, initialization, and a quick reference to the HI32 programming model. n Chapter 7, Enhanced Synchronous Serial Interface (ESSI) Enhancements, data and control signals, programming model, operating modes, initialization, exceptions, and GPIO. n Chapter 8, Serial Communication Interface (SCI) Signals, programming model, operating mod
ページ19に含まれる内容の要旨
Manual Conventions Table 1-1. High True/Low True Signal Conventions Signal/Symbol Logic State Signal State Voltage 3 PIN True Asserted V CC 2 PIN False Deasserted Ground 1. PIN is a generic term for any pin on the chip. 2. Ground is an acceptable low voltage level. See the appropriate data sheet for the range of acceptable low voltage levels (typically a TTL logic low). 3. V is an acceptable high voltage level. See the appropriate data sheet for the range of acceptable high CC voltage levels (
ページ20に含まれる内容の要旨
DSP56300 Core Features 1.3 DSP56300 Core Features All DSP56300 core family members contain the DSP56300 core and additional modules. The modules are chosen from a library of standard predesigned elements, such as memories and peripherals. New modules can be added to the library to meet customer specifications. A standard interface between the DSP56300 core and the on-chip memory and peripherals supports a wide variety of memory and peripheral configurations. In particular, the DSP56301 incl
