ページ1に含まれる内容の要旨
YMF715E
OPL3-SA3
Preliminary
OPL3 Single-chip Audio System 3
OUTLINE
YMF715E-S (OPL3-SA3) is a single audio chip that integrates OPL3 and its DAC, 16bit Sigma-delta
CODEC, MPU401 MIDI interface, joystick port, and a 3D enhanced controller including all the analog
components which is suitable for multi-media application. This LSI is fully compliant with Plug and Play
ISA 1.0a, and supports all the necessary features, i.e. 16bit address decode, more IRQs and DMAs in
compliance with PC’96. This L
ページ2に含まれる内容の要旨
YMF715E PIN CONFIGURATION YMF715E-S 75 ADFLTR 1 AVSS 74 DVSS 2 AVDD 73 SEL0 3 GP0 72 SEL1 4 GP1 71 SEL2 5 GP2 70 MP0 6 GP3 69 MP1 7 GP4 68 MP2 8 GP5 67 MP3 9 GP6 66 MP4 10 GP7 65 MP5 11 DVSS 64 MP6 12 RESET 63 MP7 13 /IOW 62 MP8 14 /IOR 61 MP9 15 DVDD 60 DVDD 16 AEN 59 /VOLUP 17 A11 58 /VOLDW 18 A10 57 A0 19 A9 56 A1 20 IRQ3 55 A2 21 IRQ5 54 X33O 22 IRQ7 53 X33I 23 IRQ9 52 X24O 24 IRQ10 51 X24I 25 IRQ11 100 pin SQFP Top View May 21, 1997 -2- SBFLTR 100 DRQ0 26 SBFLT
ページ3に含まれる内容の要旨
YMF715E PIN DESCRIPTION ISA bus interface: 36 pins name pins I/O type Size function D7-0 8 I/O TTL 24mA Data Bus A11-0 12 I TTL - Address Bus AEN 1 I TTL - Address Bus Enable /IOW 1 I Schmitt - Write Enable /IOR 1 I Schmitt - Read Enable RESET 1 I Schmitt - Reset IRQ3,5,7,9,10,11 6 T TTL 12mA Interrupt request DRQ0, 1, 3 3 T TTL 12mA DMA Request /DACK0, 1, 3 3 I TTL - DMA Acknowledge Analog Input & Output : 24 pins name pins I/O type size function OUTL 1 O - - Left mixed analog output OUTR 1 O
ページ4に含まれる内容の要旨
YMF715E Multi-purpose pins : 13 pins name pins I/O type size function SEL2-0 3 I+ CMOS - Refer to “Multi-purpose pins” section MP9-0 10 I+/O TTL 2mA Refer to “multi-purpose pins” section Others : 27 pins name pins I/O type size function GP3-0 4 IA - - Game Port GP7-4 4 I+ - Game Port Schmitt RXD 1 I+ - MIDI Data Receive Schmitt TXD 1 O TTL 4mA MIDI Data Transfer /VOLUP 1 I+ - Hardware Volume (Up) Schmitt /VOLDW 1 I+ Schmitt - Hardware Volume (Down) X33I 1 I CMOS - 33.8688 MHz X33O 1 O CMOS 2mA 3
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YMF715E BLOCK DIAGRAM May 21, 1997 -5-
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YMF715E FUNCTION OVERVIEW 1. Multi-purpose pin 1-1. Multi-purpose function OPL3-SA3 can support the various functions listed below by programming SEL2-0 pins. A. 16-bit address decode B. EEPROM interface C. Zoomed video port D. CPU and DAC interface for OPL4-ML/ML2 E. MODEM interface F. IDE CD-ROM interface Following table shows what combinations of the above functions are available for each SEL2-0 pins. SEL 16bit Dec. EEPROM ZV port OPL4-ML/ML2 MODEM CDROM Remark 0 - - - - - - Test mode (*
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YMF715E 1-2. Pin description SEL=0 SEL=1 SEL=2 SEL=3 SEL=4 SEL=5 SEL=6 SEL=7 MP0 - /MCS /MCS /EXTEN /EXTEN /MCS - /EXTEN MP1 - MIRQ MIRQ /SYNCS /SYNCS MIRQ - /SYNCS MP2 - ROMCLK ROMCLK ROMCLK BCLK_ZV A12 - A12 MP3 - ROMCS ROMCS ROMCS LRCK_ZV A13 - A13 MP4 - ROMDI ROMDI ROMDI SIN_ZV A14 - A14 MP5 - ROMDO ROMDO ROMDO /XRST A15 - A15 MP6 - /CDCS0 A12 BCLK_ML BCLK_ML BCLK_ZV - BCLK_ML MP7 - /CDCS1 A13 LRCK_ML LRCK_ML LRCK_ZV - LRCK_ML MP8 - CDIRQ A14 SIN_ML SIN_ML SIN_ZV - SIN_ML MP9 - CLKO A15 CL
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YMF715E 1-3. System Block Diagram (1) SEL=1 (Sound Card and Combo Card Add-in) SD15-8 /ENH SA2-0 SA15-12 /RESET AEN /ENL RESETDRV SD7-0 MP0 /MCS MODEM I/F } RESET MP1 MIRQ /IOW,/IOR /IOW,/IOR A11-0 SA11-0 YMF715E-S D7-0 SD7-0 (OPL3-SA3) AUX2L AUX2R EEPROM CLKO BCO YAC516 RESET LRO DO2 OPL4-ML/ML2 1. External PAL(16V8 etc.) (i) connect the signal AEN* generated by decoding SA15-12 and AEN to the AEN of OPL3- SA3. (ii) generate the /G(enable) signal for Data Bus Buffer (LS245) by decoding t
ページ9に含まれる内容の要旨
YMF715E 2. Master Clock Both 33.8688MHz and 24.576MHz are used or 14.31818MHz and clock module (ex.MK1420 by Micro Clock) are used. 3. OPL4-ML/ML2 The external DAC (YAC516) is necessary for wavetable upgrade. (2) SEL=2 (Sound Card and Combo Card for Add-in) RESET MP0 /MCS RESETDRV MODEM I/F } /IOW,/IOR MP1 MIRQ /IOW,/IOR AEN AEN MP9-6 SA15-12 YMF715E-S A11-0 SA11-0 (OPL3-SA3) D7-0 SD7-0 AUX2L X24I AUX2R X33I EEPROM CLKO BCO RESET YAC516 LRO DO2 XI OPL4-ML/ML2 MK1420 14.31818MHz 1. OPL4-ML/M
ページ10に含まれる内容の要旨
YMF715E (3) SEL=3 (Sound Card for Add-in) SA15-12 AEN* AEN AEN RESET RESETDRV BCLK_ML /IOW,/IOR MP6 /IOW,/IOR YMF715E-S LRCK_ML A11-0 MP7 SA11-0 (OPL3-SA3) SIN_ML D7-0 MP8 SD7-0 EEPROM RESET DO2 /IOW,/IOR /IOW OPL4- /IOR SA2-0 LRO ML/ML2 A2-0 D7-0 BCO SD7-0 DBDIR 1. 16bit Address Decode The signal AEN* generated by decoding SA15-12 and AEN needs to be connected to the AEN of OPL3-SA3. May 21, 1997 -10- 138 ROMCLK MP2 ROMCS MP3 245 ROMDI MP4 ROMDO MP5 /EXTEN MP0 /SYNCS /OPLCS MP1 CLKO XII MP9 T
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YMF715E (4) SEL=4 (for Notebook PC) SA15-12 AEN* BCLK_ZV AEN MP2 AEN LRCK_ZV MP3 ZV Port } SIN_ZV RESET MP4 RESETDRV /XRST Peripheral /IOW,/IOR MP5 /IOW,/IOR YMF715E-S Equipment BCLK_ML A11-0 MP6 SA11-0 (OPL3-SA3) LRCK_ML D7-0 MP7 SD7-0 SIN_ML MP8 RESET DO2 /IOW,/IOR /IOW OPL4- /IOR SA2-0 LRO ML/ML2 A2-0 D7-0 BCO SD7-0 DBDIR 1. 16bit Address Decode The signal AEN* generated by decoding SA15-12 and AEN needs to be connected to the AEN of OPL3-SA3. 2. ZV Port and OPL4-ML/ML2 I/F ZV port is supp
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YMF715E (5) SEL=5 (for Notebook PC) RESET MP0 /MCS RESETDRV MODEM I/F } /IOW,/IOR MP1 MIRQ /IOW,/IOR BCLK_ZV AEN MP6 AEN LRCK_ZV MP5-2 MP7 SA15-12 YMF715E-S ZV Port } SIN_ZV A11-0 MP8 SA11-0 (OPL3-SA3) /XRST Peripheral D7-0 MP9 SD7-0 Equipment X24I AUX2L X33I AUX2R RESET CLKO BCO YAC516 LRO DO2 XI OPL4-ML/ML2 MK1420 14.31818MHz 1. Internal DAC The internal OPL3 and the ZV Port shares the internal DAC, which is very similar to the case mentioned the previous section. (i) either internal OPL3 or
ページ13に含まれる内容の要旨
YMF715E (6) SEL=7 (for Notebook PC, Desktop PC) RESET RESETDRV /IOW,/IOR /IOW,/IOR AEN AEN BCLK_ML MP5-2 MP6 SA15-12 YMF715E-S LRCK_ML A11-0 MP7 SA11-0 (OPL3-SA3) SIN_ML D7-0 MP8 SD7-0 RESET DO2 /IOW,/IOR /IOW OPL4- /IOR SA2-0 LRO ML/ML2 A2-0 D7-0 BCO SD7-0 DBDIR May 21, 1997 -13- 245 /EXTEN MP0 /SYNCS /OPLCS MP1 CLKO XII MP9 TXD RXD TXD
ページ14に含まれる内容の要旨
YMF715E 2. ISA Interface OPL3-SA3 supports ISA Plug and Play (PnP) that frees the users from configuring the I/O address, IRQ and DMA channel. Those system resources are set automatically by the system. However even when used in Non PnP system, the configuration can be changed with software. 2-1. PnP Auto-Configuration mode OPL3-SA3 has the following I/O port to support the Plug and Play ISA. Address port: 279h Write Data Port: A79h Relocatable Read Data Port: 203h - 03FFh The following four
ページ15に含まれる内容の要旨
YMF715E 2-2. PnP ISA Configuration Register OPL3-SA3 has the following Registers defined in the PnP ISA software. 0x00 Card Control 0x22 0x30 LDN=0, SA3 Sound System 0x75 LDN=1, Joy Stick LDN=2, MODEM LDN=3, CDROM Listed below is the register map of card control register and logical device registers. For the detailed description of each register, please refer to the Plug and Play ISA Specification 1.0a Card Control Registers Index R/W D7 D6 D5 D4 D3 D2 D1 D0 00h W Set RD_DATA 01h R Serial Isol
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YMF715E Logical Device Number = 0 : SA3 Sound System 30h R/W Activate 60h R/W I/O port base address[15..8], Descriptor 0 (SB base) 61h R/W I/O port base address[7..0], Descriptor 0 (SB base) 62h R/W I/O port base address[15..8], Descriptor 1 (WSS base) 63h R/W I/O port base address[7..0], Descriptor 1 (WSS base) 64h R/W I/O port base address[15..8], Descriptor 2 (AdLib base) 65h R/W I/O port base address[7..0], Descriptor 2 (AdLib base) 66h R/W I/O port base address[15..8], Descriptor 3 (MPU bas
ページ17に含まれる内容の要旨
YMF715E Logical Device Number = 3 : CD-ROM (Optional) 30h R/W Activate 60h R/W I/O port base address [15..8], Descriptor 0 (/CDCS0) 61h R/W I/O port base address [7..0], Descriptor 0 (/CDCS0) 62h R/W I/O port base address [15..8], Descriptor 1 (/CDCS1) 63h R/W I/O port base address [7..0], Descriptor 1 (/CDCS1) 70h R/W Interrupt request level select 71h R Interrupt request type select 2-3. Recommended Resource Data The recommended resource data is the followings. (1) LDN=0:SA3 Sound System I
ページ18に含まれる内容の要旨
YMF715E IRQ-A: high-active, edge-sense Index Best Acceptable1 Acceptable2 Acceptable3 IRQ 10 7,9,10,11 5,7,9,10,11 <- IRQ-B: high-active, edge-sense Index Best Acceptable1 Acceptable2 Acceptable3 IRQ 5 5,7 5,7,9,10,11 <- DMA-A: 8bit, count by byte, type-A, B, F Index Best Acceptable1 Acceptable2 Acceptable3 DMA 0 0,1,3 0,1,3 <- DMA-B: 8bit, count by byte, type-A, B, F Index Best Acceptable1 Acceptable2 Acceptable3 DMA 1 0,1,3 0,1,3 <- (2) LDN=1:Joystick I/O (Game Port): 16bit address decode
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YMF715E (4) LDN=3:CD-ROM I/O (/CDCS0): 16bit address decode Index Best Acceptable1 Acceptable2 Acceptable3 I/O 1E8h 100-1F8h <- <- Length 8 8 <- <- Alignment - 8 <- <- I/O (/CDCS1): 16bit address decode Index Best Acceptable1 Acceptable2 Acceptable3 I/O 3EEh 306-3F6h <- <- Length 1 1 <- <- Alignment - 8 <- <- IRQ: high-active, edge-sense Index Best Acceptable1 Acceptable2 Acceptable3 IRQ 11 3,5,7,9,10,11 <- <- 2-4. Manual Configuration Mode When OPL3-SA3 is in the Wait for Key state, it can
ページ20に含まれる内容の要旨
YMF715E 3. Download Resource data When OPL3-SA3 is in the Configuration state, the host can download the resources data to EEPROM and internal SRAM via 20h: Resource Data Write. To switch OPL3-SA3 into configuration mode, there are two methods. First method is to use the normal PnP protocol. After CSN was assigned for all ISA cards by PnP soft- ware, get CSN from CM (configuration manager) and write the CSN to Wake [CSN], then OPL3-SA3 switches into configuration state. Second method is
