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PowerPC™ 405 Processor
Block Reference Guide
Embedded Development Kit
UG018 (v2.0) August 20, 2004
R
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R "Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved. CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090, XC4005, and XC5210 are registered trademarks of Xilinx, Inc. The shadow X shown above is a trademark of Xilinx, Inc. ACE Controller, ACE Flash, A.K.A. Speed, Alliance Series, AllianceCORE, Bencher, ChipScope, Configurable Logic Cell, CORE Generator, CoreLINX,
ページ3に含まれる内容の要旨
PowerPC™ 405 Processor Block Reference Guide UG018 (v2.0) August 20, 2004 The following table shows the revision history for this document. Version Revision 09/16/02 1.0 Initial Embedded Development Kit (EDK) release. 09/02/03 1.1 Updated for EDK 6.1 release 04/26/04 DRAFT Early Access release (DRAFT). 06/15/04 DRAFT Second Early Access release (DRAFT). 08/20/04 2.0 Updated to include Virtex-4 functionality. UG018 (v2.0) August 20, 2004 www.xilinx.com PowerPC™ 405 Processor Block Reference Guid
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PowerPC™ 405 Processor Block Reference Guide www.xilinx.com UG018 (v2.0) August 20, 2004 1-800-255-7778
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Table of Contents Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Typographical. . . . . . . . . . . .
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R Instruction-Side PLB Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Instruction-Side PLB I/O Signal Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Instruction-Side PLB Interface I/O Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 51 Instruction-Side PLB Interface Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Data-Side Processor Local Bus Interface
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R ISOCM Controller Instruction Fetch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 DSOCM Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 ISOCM Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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R FCM Store Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 FCM Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 FCM Decoding Using Decode Busy Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Appendix A: RISCWatch and RISCTrace Interfaces RISCWatch Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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R Preface About This Guide This guide serves as a technical reference describing the hardware interface to the ® PowerPC 405 processor block. It contains information on input/output signals, timing relationships between signals, and the mechanisms software can use to control the interface operation. The document is intended for use by FPGA and system hardware designers and by system programmers who need to understand how certain operations affect hardware external to the processor. Guide Co
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R Preface: About This Guide Additional Resources For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this website. You can also directly access these resources using the provided URLs. Resource Description/URL Tutorials Tutorials covering Xilinx design flows, from design entry to verification and debugging http://support.xilinx.com/support/techsup/tutorials/index.htm Answer Browser Database of Xilinx solution records
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R Convention Meaning or Use Example Commands that you select File Open from a menu Helvetica bold Keyboard shortcuts Ctrl+C Variables in a syntax statement for which you must ngdbuild design_name supply values See the Development System Italic font References to other manuals Reference Guide for more information. If a wire is drawn so that it Emphasis in text overlaps the pin of a symbol, the two nets are not connected. An optional entry or parameter. However, in bus ngdbuild [option_na
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R Preface: About This Guide General Conventions Table 1-1 lists the general notational conventions used throughout this document. Table 1-1: General Notational Conventions Convention Definition mnemonic Instruction mnemonics are shown in lower-case bold. variable Variable items are shown in italic. ActiveLow An overbar indicates an active-low signal. n A decimal number 0xn A hexadecimal number 0bn A binary number OBJECT A single bit in any object (a register, an instruction, an b address, or a
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R Table 1-2: PowerPC 405 Registers (Continued) Register Descriptive Name TCR Timer-control register TSR Timer-status register Terms active As applied to signals, this term indicates a signal is in a state that causes an action to occur in the receiving device, or indicates an action occurred in the sending device. An active- high signal drives a logic 1 when active. An active-low signal drives a logic 0 when active. assert As applied to signals, this term indicates a signal is driven to its
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R Preface: About This Guide exception An abnormal event or condition that requires the processor’s attention. They can be caused by instruction execution or an external device. The processor records the occurrence of an exception and they often cause an interrupt to occur. fill buffer A buffer that receives and sends data and instructions between the processor and PLB. It is used when cache misses occur and when access to non-cacheable memory occurs. flush A cache operation that involves wr
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R OEA The PowerPC operating-environment architecture, which defines the memory-management model, supervisor-level registers and instructions, synchronization requirements, the exception model, and the time-base resources as seen by supervisor programs. on chip In system-on-chip implementations, this indicates on the same FPGA chip as the processor core, but external to the processor core. pending As applied to interrupts, this indicates that an exception occurred, but the interrupt is dis
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R Preface: About This Guide UISA The PowerPC user instruction-set architecture, which defines the base user-level instruction set, registers, data types, the memory model, the programming model, and the exception model as seen by user programs. user mode The operating mode typically used by application software. Privileged operations are not allowed in user mode, and software can access a restricted set of registers and memory. VEA The PowerPC virtual-environment architecture, which defines
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R Chapter 1 Introduction to the PowerPC 405 Processor The PowerPC 405 is a 32-bit implementation of the PowerPC embedded-environment architecture that is derived from the PowerPC architecture. Specifically, the PowerPC 405 is an embedded PowerPC 405D5 (for Virtex-II Pro) or 405F6 (for Virtex-4) processor core. The term processor block is used throughout this document to refer to the combination of a PPC405D5 or PPC405F6 core, on-chip memory logic (OCM), an APU controller (Virtex-4 only), a
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R Chapter 1: Introduction to the PowerPC 405 Processor Table 1-1: Three Levels of PowerPC Architecture User Instruction-Set Architecture Virtual Environment Architecture Operating Environment (UISA) (VEA) Architecture (OEA) Defines the architecture level to Defines additional user-level Defines supervisor-level which user-level (sometimes functionality that falls outside resources typically required by referred to as problem state) typical user-level software an operating system softwar
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R Special-purpose registers for controlling the use of debug resources, timer resources, interrupts, real-mode storage attributes, memory-management facilities, and other architected processor resources. A device-control-register address space for managing on-chip peripherals such as memory controllers. A dual-level interrupt structure and interrupt-control instructions. Multiple timer resources. Debug resources that enable hardware-debug and software-debug functions such as instru
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R Chapter 1: Introduction to the PowerPC 405 Processor Table 1-2: OEA Features of the PowerPC Embedded-Environment Architecture Operating Features Environment Register model Privileged special-purpose registers (SPRs) and instructions for accessing those registers Device control registers (DCRs) and instructions for accessing those registers Storage model Privileged cache-management instructions Storage-attribute controls Address translation and memory protection Privileged TLB-man
