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Preliminary Information
AMD Athlon™ Processor Model 4
Revision Guide
Publication # 23614 Rev: K
Issue Date: October 2003
ページ2に含まれる内容の要旨
Preliminary Information © 2001–2003 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise,
ページ3に含まれる内容の要旨
Preliminary Information 23614K—October 2003 AMD Athlon™ Processor Model 4 Revision Guide Revision History Date Rev Description October 2003 K Revised erratum #24. June 2003 J Added erratum #24. December 2002 I Added errata #21–23. July 2002 H Added erratum #20. March 2002 G Added erratum #17. Removed OPN information. Added errata items 13, 14, 15, 16. Added information on silicon April 2001 F revision A9. 3
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Preliminary Information AMD Athlon™ Processor Model 4 Revision Guide 23614K—October 2003 AMD Athlon™ Processor Model 4 Revision Guide The purpose of the AMD Athlon™ Processor Model 4 Revision Guide is to communicate updated product information on the AMD Athlon™ processor model 4 to designers of computer systems and software developers. This guide consists of three sections: ■ Product Errata: This section, which starts on page 5, provides a detailed description of product errata, including pote
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Preliminary Information 23614K—October 2003 AMD Athlon™ Processor Model 4 Revision Guide 1 Product Errata This section documents AMD Athlon processor model 4 product errata. The errata are divided into categories to assist referencing particular errata. A unique tracking number for each erratum has been assigned within this document for user convenience in tracking the errata within specific revision levels. Table 1 cross-references the revisions of the processor to each erratum. An “X” indicate
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Preliminary Information AMD Athlon™ Processor Model 4 Revision Guide 23614K—October 2003 5 MCA Bus Unit Control Register MSR 408H Returns Incorrect Information Products Affected. A4, A5, A6, A7, A9 Normal Specified Operation. System reads to MSR 408h, MCA Bus Unit Control Register MC2_CTL, should return correct information—the lower 32 bits in EAX and all zeros for the upper 32 bits in EDX. Non-conformance. A read to the Machine Check Architecture (MCA) Bus Unit Control MSR 408h (MC2_CTL) retur
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Preliminary Information 23614K—October 2003 AMD Athlon™ Processor Model 4 Revision Guide 10 Resistance Value of the ZN and ZP Pins Products Affected. A4, A5 Normal Specified Operation. The ZN and ZP pins are specified such that the AMD system bus output drivers autocompensate to whatever resistance value is applied between ZN and VDD and ZP and VSS. Non-conformance. The AMD system bus driver impedance is approximately 20 ohms higher than the applied resistor value. Potential Effect on System.
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Preliminary Information AMD Athlon™ Processor Model 4 Revision Guide 23614K—October 2003 11 PLL Overshoot on Wake-Up from Disconnect Causes Auto-Compensation Circuit to Fail Products Affected. A4, A5, A6, A7, A9 Normal Specified Operation. The AMD Athlon processor model 4 PLL should return to the normal operating frequency when reconnecting to the system bus after a disconnect where the PLL was reduced to a lower operating frequency. Non-conformance. The AMD Athlon processor model 4 PLL can ex
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Preliminary Information 23614K—October 2003 AMD Athlon™ Processor Model 4 Revision Guide 13 Instruction Execution Deadlock Products Affected. A4, A5, A6, A7 Normal Specified Operation. Legitimate instruction sequences should execute as specified. Non-conformance. Under rare and unlikely conditions, the load-store unit, instruction scheduler and effective address generation unit interact in such a way that deadlock a occurs, preventing further instruction execution. Potential Effect on Syste
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Preliminary Information AMD Athlon™ Processor Model 4 Revision Guide 23614K—October 2003 14 Processors with Half-Frequency Multipliers May Hang Upon Wake-up from Disconnect Products Affected. A4, A5, A6, A7, A9 Normal Specified Operation. The processor should reconnect to the system bus upon wake-up after a disconnect while in the C2 and C3 ACPI low-power states. Non-conformance. The processor uses a special circuit to wake up from a low-power state and reconnect to the system bus when the nomi
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Preliminary Information 23614K—October 2003 AMD Athlon™ Processor Model 4 Revision Guide 15 Processor Does Not Support Reliable Microcode Patch Mechanism Products Affected. A9 Normal Specified Operation. The processor should function properly after a microcode patch is loaded. Non-conformance. The processor has the patch RAM BIST function disabled. Since BIST is not run on the patch RAM, reliable operation of the patch RAM cannot be assured. Therefore it should not be used. Potential Effect on
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Preliminary Information AMD Athlon™ Processor Model 4 Revision Guide 23614K—October 2003 16 INVLPG Instruction Does Not Flush Entire Four-Megabyte Page Properly with Certain Linear Addresses Products Affected. A4, A5, A6, A7, A9 Normal Specified Operation. After executing an INVLPG instruction the TLB should not contain any translations for any part of the page frame associated with the designated logical address. Non-conformance. When the logical address designated by the INVLPG instruction i
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Preliminary Information 23614K—October 2003 AMD Athlon™ Processor Model 4 Revision Guide 17 Code Modifications that Coincide with Level 2 Instruction TLB Translations May Escape Detection Resulting in Stale Code Execution Products Affected. A4, A5, A6, A7, A9 Normal Specified Operation. Self-modifying code sequences should be correctly detected and handled in a manner that results in correct canonical results; stale code should not be executed. Non-conformance. If the following events occur wi
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Preliminary Information AMD Athlon™ Processor Model 4 Revision Guide 23614K—October 2003 20 A Speculative SMC Store Followed by an Actual SMC Store May Cause One-Time Stale Execution Products Affected. A4, A5, A6, A7, A9 Normal Specified Operation. Self-modifying code sequences should be correctly detected and handled in a manner consistent with canonical results; stale code should not be executed. Non-conformance. The following scenario can result in a one-time execution of stale instructions
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Preliminary Information 23614K—October 2003 AMD Athlon™ Processor Model 4 Revision Guide 21 Real Mode RDPMC with Illegal ECX May Cause Unpredictable Operation Products Affected. A4, A5, A6, A7, A9 Normal Specified Operation. Illegal values of ECX (that is, ECX>3) for the RDPMC (Read Performance Monitor Counter) instruction cause the processor to take a general protection exception. Non-conformance. If the RDPMC is executed in real mode with a specific illegal value of ECX=4, then the processor
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Preliminary Information AMD Athlon™ Processor Model 4 Revision Guide 23614K—October 2003 22 Using Task Gates With Breakpoints Enabled May Cause Unexpected Faults Products Affected. A4, A5, A6, A7, A9 Normal Specified Operation. Task gates should correctly use the TSS selector out of the task gate for CALL and JMP instructions. Non-conformance. When a task gate is used by a CALL or JMP instruction and any debug breakpoint is enabled through the DR7.LE or GE bits, the processor may, under certain
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Preliminary Information 23614K—October 2003 AMD Athlon™ Processor Model 4 Revision Guide 23 Single Step Across I/O SMI Skips One Debug Trap Products Affected. A4, A5, A6, A7, A9 Normal Specified Operation. When single stepping (with EFLAGS.TF) across an IN or OUT instruction that detects an SMI, the processor correctly defers taking the debug trap and instead enters SMM. Upon RSM (without I/O restart), the processor should immediately enter the debug trap handler. Non-conformance. Under this
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Preliminary Information AMD Athlon™ Processor Model 4 Revision Guide 23614K—October 2003 24 Software Prefetches May Report A Page Fault Products Affected. A4, A5, A6, A7, A9 Normal Specified Operation. Software prefetches should not report page faults if they encounter them. Non-conformance. Software prefetch instructions are defined to ignore page faults. Under highly specific and detailed internal circumstances, a prefetch instruction may report a page fault if both of the following conditio
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Preliminary Information 23614K—October 2003 AMD Athlon™ Processor Model 4 Revision Guide Because the actual errata is infrequent, it does not produce an excessive number of page faults that affect system performance. Therefore a page fault from a prefetch instruction for an address within an "accessible" page does not require any general workaround. Software can minimize the occurrence of the errata by issuing only one prefetch instruction per cache- line (a naturally-aligned 64-byte quantity)
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Preliminary Information AMD Athlon™ Processor Model 4 Revision Guide 23614K—October 2003 2 Revision Determination Table 2 shows the AMD Athlon processor model 4 identification number returned by the CPUID instruction for each revision of the processor. Table 2. CPUID Values for the Revisions of the AMD Athlon™ Processor Model 4 Revision CPUID A4 642 A5 642 A6 642 A7 642 A9 644 20
