ページ1に含まれる内容の要旨
PMC
Pm25LV512 / Pm25LV010
512 Kbit / 1 Mbit 3.0 Volt-only, Serial Flash Memory
With 25 MHz SPI Bus Interface
FEATURES
Block Write Protection
Single Power Supply Operation
- The Block Protect (BP1, BP0) bits allow part or entire
- Low voltage range: 2.7 V - 3.6 V
of the memory to be configured as read-only.
• Memory Organization
Hardware Data Protection
- Pm25LV512: 64K x 8 (512 Kbit)
- Write Protect (WP#) pin will inhibit write operations
- Pm25LV010: 128K x 8 (1 Mbit)
to the status re
ページ2に含まれる内容の要旨
PMC Pm25LV512/010 CONNECTION DIAGRAMS CE# 1 8 Vcc CE# 1 8 Vcc SO 2 7 HOLD# SO 2 7 HOLD# Top View WP# 3 6 SCK WP# 6 SCK 3 4 5 GND SI GND 5 4 SI 8-Pin SOIC 8-Contact WSON PIN DESCRIPTIONS SE YMBOLTN YP DESCRIPTIO Chip Enable: CE# goes low activates the device's internal circuitries for device operation. CE# goes high deselects the device and switches into CT E# INPU standby mode to reduce the power consumption. When the device is not selected, da
ページ3に含まれる内容の要旨
PMC Pm25LV512/010 PRODUCT ORDERING INFORMATION Pm25LVxxx -25 S C E Environmental Attribute E = Lead-free (Pb-free) Package Blank = Standard Package Temperature Range C = Commercial (0°C to +85°C) Package Type S = 8-pin SOIC (8S) Q = 8-contact WSON (8Q) Operating Speed 25 MHz PMC Device Number Pm25LV512 (512 Kbit) Pm25LV010 (1 Mbit) Part Number Operating Frequency (MHz) Package Temperature Range Pm25LV512-25SCE 8S 25 Pm25LV512-25SC 8Q Commercial Pm25LV512-25QCE o o (0 C to + 85
ページ4に含まれる内容の要旨
PMC Pm25LV512/010 BLOCK DIAGRAM SPI Chip Block Diagram High Voltage Generator Control Logic Instruction Decoder Serial /Parallel convert Logic 2KBit Page Buffer Status Address Latch Register & Counter Memory Array X-DECODER Programmable Microelectronics Corp. Issue Date: February, 2004, Rev: 1.4 4 Y-DECODER
ページ5に含まれる内容の要旨
PMC Pm25LV512/010 SERIAL INTERFACE DESCRIPTION Pm25LV512/010 can be driven by a microcontroller on the SPI bus as shown in Figure 1. The serial communication term definitions are in the following section. MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the Pm25LV512/010 always operates as a slave. TRANSMITTER/RECEIVER: The Pm25LV512/010 has separate pins designated for data transmission (SO) and reception (Sl). MSB: The Most Signi
ページ6に含まれる内容の要旨
PMC Pm25LV512/010 SERIAL INTERFACE DESCRIPTION (CONTINUED) SPI MODES These devices can be driven by microcontroller with its available from the falling edge of Serial Clock (SCK). SPI peripheral running in either of the two following modes: Mode 0 = (0, 0) The difference between the two modes, as shown in Mode 3 = (1, 1) Figure 2, is the clock polarity when the bus master is in Stand-by mode and not transfering data: For these two modes, input data is latched in on the - Clock remains at 0 (SCK
ページ7に含まれる内容の要旨
PMC Pm25LV512/010 DEVICE OPERATION The Pm25LV512/010 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The Pm25LV512/010 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 1. All instructions, addresses, and data are transferred with the MSB first and start with a high- to-low transition. Write is defined as program and/or erase in this specification.
ページ8に含まれる内容の要旨
PMC Pm25LV512/010 WRITE ENABLE (WREN): The device will power up in the write disable state when Vcc is applied. All write instructions must therefore be preceded by the WREN instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the WRDI instruction disables all write commands. The WRDI instruction is independent of the status of the WP# pin. READ STATUS REGISTER (RDSR): The RDSR instruction provides access to the status register. The READY/ BUSY and write enable st
ページ9に含まれる内容の要旨
PMC Pm25LV512/010 Table 5. Block Write Protect Bits S2 tatus Register BitsP0 m25LV51 Pm25LV01 Array Addresses Locked-out Array Addresses Locked-out Level B0 P1 BP Locked Out Block(s) Locked Out Block(s) 00 0 Ne one Non 10 (1/4) 1 Ne one Non04 18000 - 01FFFF Block 21 (1/2) 0 04 10000 - 01FFFF Block 3, All Blocks All Blocks 31 (All) 1 000000-00FFFF 000000 - 01FFFF (1 - 2) (1 - 4) The WRSR instruction also allows the user to enable or disable the Write Protect (WP#) pin through the use of the Write
ページ10に含まれる内容の要旨
PMC Pm25LV512/010 READ: Reading the Pm25LV512/010 via the SO (Serial Output) pin requires the following sequence. After the CE# line is pulled low to select a device, the READ instruction is transmitted via the Sl line followed by the byte address to be read (Refer to Table 7). Upon completion, any data on the Sl line will be ignored. The data (D7-D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CE# line should be driven high after the data c
ページ11に含まれる内容の要旨
PMC Pm25LV512/010 SECTOR_ERASE, BLOCK_ERASE: Before a byte can be reprogrammed, the sector/block which contains the byte must be erased. In order to erase the Pm25LV512/010, two separate instructions must be executed. First, the device must be write enabled via the WREN instruction. Then the SECTOR ERASE or BLOCK ERASE instruction can be executed. Table 8. Block Addresses Bk lock AddressPk m25LV512 Bloc Pm25LV010 Bloc 01 00000 to 007FFF B1 lock Block 02 08000 to 00FFFF B2 lock Block 0A 10000 to
ページ12に含まれる内容の要旨
PMC Pm25LV512/010 (1) ABSOLUTE MAXIMUM RATINGS o o Temperature Under Bias -65 C to +125 C o o Storage Temperature -65 C to +125 C o S0 tandard Package 24 C 3 Seconds Surface Mount Lead Soldering Temperature o L0 ead-free Package 26 C 3 Seconds (2) Input Voltage with Respect to Ground on All Pins -0.5 V to V + 0.5 V CC All Output Voltage with Respect to Ground -0.5 V to V + 0.5 V CC (2) V -0.5 V to +6.0 V CC Notes: 1. Stresses under those listed in “Absolute Maximum Ratings” may cause permanent
ページ13に含まれる内容の要旨
PMC Pm25LV512/010 DC CHARACTERISTICS Applicable over recommended operating range from: T = 0°C to +85°C, V = +2.7 V to +3.6 V (unless otherwise noted). AC CC Condition Symbol Parameter Min Typ Max Units V = 3.6V at 25 MHz, SO = Open I Vcc Active Read Current 10 15 mA CC1 CC I Vcc Program/Erase Current V = 3.6V at 25 MHz, SO = Open 15 30 mA CC CC2 V = 3.6V, CE# = V I Vcc Standby Current CMOS 0.1 5 μA CC CC SB1 V = 3.6V, CE# = V to V I Vcc Standby Current TTL 0.05 3 mA CC IH CC SB2 V = 0V to V I I
ページ14に含まれる内容の要旨
PMC Pm25LV512/010 AC CHARACTERISTICS Applicable over recommended operating range from T = 0°C to +85°C, V = +2.7 V to +3.6 V A CC C = 1TTL Gate and 30 pF (unless otherwise noted). L Sr ymbolPn aramete Mp i Tx y Ms a Unit Clock Frequency for f 052z MH FR FAST_READ fC0 lock Frequency for READ instructions 2z0 MH R t Input Rise Time 2s 0 n RI t Input Fall Time 2s 0 n FI tS0 CK High Time 2s n CKH tS0 CK Low Time 2s n CKL tC5 E High Time 2s n CEH tC5 E Setup Time 2s n CS tC5 E Hold Time 2s n CH tD5 a
ページ15に含まれる内容の要旨
PMC Pm25LV512/010 AC CHARACTERISTICS (CONTINUED) (1) AC WAVEFORMS t CEH V IH CE# V IL t t CS CH V IH t SCK t CKL CKH V IL t t DS DH V IH SI VALID IN V IL t t t OH DIS V V OH HI-Z HI-Z SO V OL Note: 1. For SPI Mode 0 (0,0) OUTPUT TEST LOAD INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL 3.3 V 3.0 V AC 1.8 K Input 1.5 V Measurement Level OUTPUT PIN 0.0 V 1.3 K 30 pF Programmable Microelectronics Corp. Issue Date: February, 2004, Rev: 1.4 15
ページ16に含まれる内容の要旨
PMC Pm25LV512/010 AC CHARACTERISTICS (CONTINUED) HOLD Timing CE# t t HD HD SCK t HS t HS HOLD# t HZ SO t LZ PIN CAPACITANCE ( f = 1 MHz, T = 25°C ) Tx yp Ms aUs nit Condition C 46 pV F = 0 V IN IN C 821FpV = 0 V OUT OUT Note: These parameters are characterized but not 100% tested. Programmable Microelectronics Corp. Issue Date: February, 2004, Rev: 1.4 16
ページ17に含まれる内容の要旨
PMC Pm25LV512/010 TIMING DIAGRAMS RDID Timing CE# 01 7 8 9 31 38 39 46 47 54 SCK INSTRUCTION 3 Dummy Bytes 1010 1011b SI HIGH IMPEDANCE SO Manufacture ID1 Device ID Manufacture ID2 WREN Timing CE# SCK SI INSTRUCTION = 0000 0110b HI-Z SO WRDI Timing CE# SCK SI INSTRUCTION = 0000 0100b HI-Z SO nnnnnnN Programmable Microelectronics Corp. Issue Date: February, 2004, Rev: 1.4 17
ページ18に含まれる内容の要旨
PMC Pm25LV512/010 RDSR Timing CE# 12 3 7 9 0 4 56 8 10 11 12 13 14 SCK SI INSTRUCTION = 0000 0101b DATA OUT HIGH IMPEDANCE SO 765 4 3 2 1 0 MSB WRSR Timing CE# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK DATA IN SI 32 INSTRUCTION = 0000 0001b 76 5 4 10 HIGH IMPEDANCE SO READ Timing CE# 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34 35 36 37 38 SCK 3-BYTE ADDRESS ... SI 23 22 21 3 2 1 0 INSTRUCTION = 0000 0011b HIGH IMPEDANCE SO 76 5 4 3 2 1 0 Programmable Microelectronics Corp. Issue Date: Februar
ページ19に含まれる内容の要旨
PMC Pm25LV512/010 FAST READ Timing CE# 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 SCK 3-BYTE ADDRESS ... SI 23 22 21 3 2 1 0 INSTRUCTION = 0000 1011b HIGH IMPEDANCE SO CE# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK DUMMY BYTE 3 765 4 2 1 0 SI DATA OUT 1 DATA OUT 2 HIGH IMPEDANCE SO 76 5 4 3 2 1 0 76 5 4 3 2 1 0 PAGE PROGRAM Timing CE# 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34 SCK 1st BYTE DATA-IN 256th BYTE DATA-IN 3-BYTE ADDRESS SI INSTRUCTION = 0000 0010b 23 22 21 3214 07 6 53 2 10 HI
ページ20に含まれる内容の要旨
PMC Pm25LV512/010 SECTOR ERASE Timing CE# 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 SCK 3-BYTE ADDRESS ... SI INSTRUCTION = 1101 0111b 23 22 21 3 2 1 0 HIGH IMPEDANCE SO BLOCK ERASE Timing CE# 0 1 2 3 4 5 67 89 10 11 28 29 30 31 SCK 3-BYTE ADDRESS ... SI INSTRUCTION = 1101 1000b 23 22 21 3 2 1 0 HIGH IMPEDANCE SO CHIP ERASE Timing CE# 012 34567 SCK INSTRUCTION = 1100 0111b SI HIGH IMPEDANCE SO Programmable Microelectronics Corp. Issue Date: February, 2004, Rev: 1.4 20
