ページ1に含まれる内容の要旨
a
DSP Microcomputer
ADSP-2186
FUNCTIONAL BLOCK DIAGRAM
FEATURES
PERFORMANCE
30 ns Instruction Cycle Time 33 MIPS Sustained POWER-DOWN
CONTROL
FULL MEMORY
Performance
MODE
MEMORY
PROGRAMMABLE
DATA ADDRESS
Single-Cycle Instruction Execution I/O
8K 24 8K 16 EXTERNAL
GENERATORS PROGRAM
AND
PROGRAM DATA ADDRESS
SEQUENCER
Single-Cycle Context Switch FLAGS
DAG 1 DAG 2 MEMORY MEMORY BUS
3-Bus Architecture Allows Dual Operand Fetches in
EXTERNAL
DATA
PROGRAM MEMORY ADDRESS
Every Instruction Cycle
BUS
ページ2に含まれる内容の要旨
ADSP-2186 ® EZ-ICE * connector, emulation can be supported in final board biased rounding, result free ALU operations, I/O memory trans- designs. fers and global interrupt masking for increased flexibility. ® The EZ-ICE * performs a full range of functions, including: Fabricated in a high speed, double metal, low power, CMOS process, the ADSP-2186 operates with a 30 ns instruction cycle • In-target operation time. Every instruction can execute in a single processor cycle. • Up to 20 breakpoints
ページ3に含まれる内容の要旨
ADSP-2186 and the power-down circuitry. There is also a master RESET The shifter can be used to efficiently implement numeric signal. The two serial ports provide a complete synchronous format control including multiword and block floating-point serial interface with optional companding in hardware and a representations. wide variety of framed or frameless data transmit and receive The internal result (R) bus connects the computational units so modes of operation. the output of any unit may be t
ページ4に含まれる内容の要旨
ADSP-2186 concurrently on multiplexed pins. In cases where pin func- Memory Interface Pins tionality is reconfigurable, the default state is shown in plain The ADSP-2186 processor can be used in one of two modes: text; alternate functionality is shown in italics. Full Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, Common-Mode Pins which allows IDMA operation with limited external addressing # Input/ capabilities. The operating mode is
ページ5に含まれる内容の要旨
ADSP-2186 To minimize power consumption during power-down, configure The IFC register is a write-only register used to force and clear the programmable flag as an output when connected to a three- interrupts. stated buffer. This ensures that the pin will be held at a constant On-chip stacks preserve the processor status and are automati- level and not oscillate should the three-state driver’s level hover cally maintained during interrupt handling. The stacks are twelve around the logic switching
ページ6に含まれる内容の要旨
ADSP-2186 FULL MEMORY MODE Idle When the ADSP-2186 is in the Idle Mode, the processor waits ADSP-2186 A 14 13-0 1/2x CLOCK CLKIN indefinitely in a low power state until an interrupt occurs. When OR ADDR13-0 CRYSTAL XTAL D A0-A21 an unmasked interrupt occurs, it is serviced; execution then 23-16 FL0-2 BYTE continues with the instruction following the IDLE instruction. 24 D 15-8 PF3 MEMORY DATA23-0 DATA In Idle mode IDMA, BDMA and autobuffer cycle steals still /PF7 /PF4 occur. /PF5 A /PF6 10-0 Slo
ページ7に含まれる内容の要旨
ADSP-2186 Clock Signals The master reset sets all internal stack pointers to the empty The ADSP-2186 can be clocked by either a crystal or a TTL- stack condition, masks all interrupts and clears the MSTAT compatible clock signal. register. When RESET is released, if there is no pending bus request and the chip is configured for booting, the boot-loading The CLKIN input cannot be halted, changed during operation sequence is performed. The first instruction is fetched from or operated below the sp
ページ8に含まれる内容の要旨
ADSP-2186 There are 8K words of memory accessible internally when the There are 8160 words of memory accessible internally when the PMOVLAY register is set to 0. When PMOVLAY is set to some- DMOVLAY register is set to 0. When DMOVLAY is set to thing other than 0, external accesses occur at addresses 0x2000 something other than 0, external accesses occur at addresses through 0x3FFF. The external address is generated as shown in 0x0000 through 0x1FFF. The external address is generated as Table II.
ページ9に含まれる内容の要旨
ADSP-2186 Byte Memory When the BWCOUNT register is written with a nonzero value, The byte memory space is a bidirectional, 8-bit-wide, external the BDMA circuit starts executing byte memory accesses with memory space used to store programs and data. Byte memory is wait states set by BMWAIT. These accesses continue until the accessed using the BDMA feature. The byte memory space count reaches zero. When enough accesses have occurred to consists of 256 pages, each of which is 16K × 8. create a des
ページ10に含まれる内容の要旨
ADSP-2186 Bootstrap Loading (Booting) gram execution to be held off until all 32 words are loaded into The ADSP-2186 has two mechanisms to allow automatic load- on-chip program memory. Execution then begins at address 0. ing of the internal program memory after reset. The method for The ADSP-2100 Family development software (Revision 5.02 booting is controlled by the Mode A, B and C configuration bits and later) fully supports the BDMA booting feature and can as shown in Table VI. These four sta
ページ11に含まれる内容の要旨
ADSP-2186 configured as an input is synchronized to the ADSP-2186’s • Sixteen condition codes are available. For conditional jump, clock. Bits that are programmed as outputs will read the value call, return or arithmetic instructions, the condition can be being output. The PF pins default to input during reset. checked and the operation executed in the same instruction cycle. In addition to the programmable flags, the ADSP-2186 has five • Multifunction instructions allow parallel execution of an
ページ12に含まれる内容の要旨
ADSP-2186 ® trouble manufacturing your system as DSP components statisti- The EZ-ICE * connects to your target system via a ribbon cable cally vary in switching characteristic and timing requirements and a 14-pin female plug. The female plug is plugged onto the within published limits. 14-pin connector (a pin strip header) on the target board. ® Restriction: All memory strobe signals on the ADSP-2186 (RD, Target Board Connector for EZ-ICE * Probe ® WR, PMS, DMS, BMS, CMS and IOMS) used in your t
ページ13に含まれる内容の要旨
ADSP-2186 ADSP-2186 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS K Grade B Grade Parameter Min Max Min Max Unit V 4.5 5.5 4.5 5.5 V DD T 0 +70 –40 +85 °C AMB ELECTRICAL CHARACTERISTICS K/B Grades Parameter Test Conditions Min Typ Max Unit 1, 2 V Hi-Level Input Voltage @ V = max 2.0 V IH DD V Hi-Level CLKIN Voltage @ V = max 2.2 V IH DD 1, 3 V Lo-Level Input Voltage @ V = min 0.8 V IL DD 1, 4, 5 V Hi-Level Output Voltage @ V = min OH DD I = –0.5 mA 2.4 V OH @ V = min DD 6 I = –100 μA V – 0.3 V
ページ14に含まれる内容の要旨
ADSP-2186 ABSOLUTE MAXIMUM RATINGS* Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V DD Output Voltage Swing . . . . . . . . . . . . . –0.3 V to V + 0.3 V DD Operating Temperature Range (Ambient) . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (5 sec) TQFP . . . . . . . . . . . . . . . +280°C *Stresses above those listed under Absolute Max
ページ15に含まれる内容の要旨
ADSP-2186 1, 3, 4, 5 ENVIRONMENTAL CONDITIONS 2186 POWER, INTERNAL 450 Ambient Temperature Rating: V = 5.5V 425 DD 430mW T =T – (PD x θ ) AMB CASE CA 400 370mW T = Case Temperature in °C CASE 375 PD = Power Dissipation in W 350 330mW 325mW θ = Thermal Resistance (Case-to-Ambient) 325 V = 5.0V CA DD 300 θ = Thermal Resistance (Junction-to-Ambient) 275mW JA 275 θ = Thermal Resistance (Junction-to-Case) JC 245mW 235mW 250 V = 4.5V DD 225 195mW 200 Package u u u JA JC CA 175mW 175 150 TQFP 50°C/W 2
ページ16に含まれる内容の要旨
ADSP-2186 CAPACITIVE LOADING t , is dependent on the capacitive load, C , and the current DECAY L Figures 9 and 10 show the capacitive loading characteristics of load, i , on the output pin. It can be approximated by the fol- L the ADSP-2186. lowing equation: 30 C × 0.5V L t = T = +85°C DECAY i = 4.5V V L DD 25 from which t = t – t 20 DIS MEASURED DECAY is calculated. If multiple pins (such as the data bus) are dis- 15 abled, the measurement value is that of the last pin to stop driving. 10
ページ17に含まれる内容の要旨
ADSP-2186 TIMING PARAMETERS Parameter Min Max Unit Clock Signals and Reset Timing Requirements: t CLKIN Period 60 [50] 150 ns CKI t CLKIN Width Low 20 ns CKIL t CLKIN Width High 20 ns CKIH Switching Characteristics: t CLKOUT Width Low 0.5 t – 7 ns CKL CK t CLKOUT Width High 0.5 t – 7 ns CKH CK t CLKIN High to CLKOUT High 0 20 ns CKOH Control Signals Timing Requirements: 1 t RESET Width Low 5 t ns RSP CK t Mode Setup Before RESET High 2 ns MS t Mode Setup After RESET High 5 ns MH NOTES Paramete
ページ18に含まれる内容の要旨
ADSP-2186 TIMING PARAMETERS Parameter Min Max Unit Interrupts and Flag Timing Requirements: 1, 2, 3, 4 t IRQx, FI, or PFx Setup before CLKOUT Low 0.25 t + 15 ns IFS CK 1, 2, 3, 4 t IRQx, FI, or PFx Hold after CLKOUT High 0.25 t ns IFH CK Switching Characteristics: 5 t Flag Output Hold after CLKOUT Low 0.25 t – 7 ns FOH CK 5 t Flag Output Delay from CLKOUT Low 0.5 t + 5 ns FOD CK NOTES 1 If IRQx and FI inputs meet t and t setup/hold requirements, they will be recognized during the current clock
ページ19に含まれる内容の要旨
ADSP-2186 Parameter Min Max Unit Bus Request/Grant Timing Requirements: 1 t BR Hold after CLKOUT High 0.25 t + 2 ns BH CK 1 t BR Setup before CLKOUT Low 0.25 t + 17 ns BS CK Switching Characteristics: t CLKOUT High to xMS, RD, WR Disable 0.25 t + 10 ns SD CK t xMS, RD, WR Disable to BG Low 0 ns SDB t BG High to xMS, RD, WR Enable 0 ns SE t xMS, RD, WR Enable to CLKOUT High 0.25 t – 7 ns SEC CK 2 t xMS, RD, WR Disable to BGH Low0ns SDBH 2 t BGH High to xMS, RD, WR Enable0ns SEH NOTES xMS = PMS,
ページ20に含まれる内容の要旨
ADSP-2186 TIMING PARAMETERS Parameter Min Max Unit Memory Read Timing Requirements: t RD Low to Data Valid 0.5 t – 9 + w ns RDD CK t A0–A13, xMS to Data Valid 0.75 t – 10.5 + w ns AA CK t Data Hold from RD High 0 ns RDH Switching Characteristics: t RD Pulse Width 0.5 t – 5 + w ns RP CK t CLKOUT High to RD Low 0.25 t – 5 0.25 t + 7 ns CRD CK CK t A0–A13, xMS Setup before RD Low 0.25 t – 6 ns ASR CK t A0–A13, xMS Hold after RD Deasserted 0.25 t – 3 ns RDA CK t RD High to RD or WR Low 0.5 t – 5 ns
