ページ1に含まれる内容の要旨
CY7C1018DV33
1-Mbit (128K x 8) Static RAM
[1]
Features Functional Description
• Pin- and function-compatible with CY7C1018CV33 The CY7C1018DV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
• High speed
expansion is provided by an active LOW Chip Enable (CE), an
—t = 10 ns
AA
active LOW Output Enable (OE), and tri-state drivers. This
• Low Active Power device has an automatic power-down feature that significantly
reduces power consumption when deselecte
ページ2に含まれる内容の要旨
CY7C1018DV33 Selection Guide –10 (Industrial) Unit Maximum Access Time 10 ns Maximum Operating Current 60 mA Maximum Standby Current 3 mA [2] DC Input Voltage ................................ –0.3V to V + 0.3V Maximum Ratings CC Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage........................................... > 2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage
ページ3に含まれる内容の要旨
CY7C1018DV33 [3] Capacitance Parameter Description Test Conditions Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, V = 3.3V 8 pF IN A CC C Output Capacitance 8 pF OUT [3] Thermal Resistance 400-Mil Parameter Description Test Conditions Unit Wide SOJ Θ Thermal Resistance Still Air, soldered on a 3 × 4.5 inch, 57.61 °C/W JA (Junction to Ambient) four-layer printed circuit board Θ Thermal Resistance 40.53 °C/W JC (Junction to Case) [4] AC Test Loads and Waveforms ALL INPUT PULSES 3.0V Z = 50 Ω
ページ4に含まれる内容の要旨
CY7C1018DV33 [5] AC Switching Characteristics Over the Operating Range –10 (Industrial) Parameter Description Unit Min. Max. Read Cycle [6] t V (typical) to the first access 100 µs power CC t Read Cycle Time 10 ns RC t Address to Data Valid 10 ns AA t Data Hold from Address Change 3 ns OHA t CE LOW to Data Valid 10 ns ACE t OE LOW to Data Valid 5 ns DOE t OE LOW to Low-Z 0 ns LZOE [7, 8] t OE HIGH to High-Z 5ns HZOE [8] t CE LOW to Low-Z 3ns LZCE [7, 8] t CE HIGH to High-Z 5ns HZCE [9] t CE LOW
ページ5に含まれる内容の要旨
CY7C1018DV33 Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions Min. Max. Unit V V for Data Retention 2 V DR CC I Data Retention Current V = V = 2.0V, CE > V – 0.3V, 3mA CCDR CC DR CC V > V – 0.3V or V < 0.3V IN CC IN [3] t Chip Deselect to Data Retention Time 0 ns CDR [12] t Operation Recovery Time t ns R RC Data Retention Waveform DATA RETENTION MODE 3.0V 3.0V V V > 2V CC DR t t CDR R CE Switching Waveforms [13, 14] Read Cycle No. 1 (Address Transition
ページ6に含まれる内容の要旨
CY7C1018DV33 Switching Waveforms (continued) [16, 17] Write Cycle No. 1 (CE Controlled) t WC ADDRESS t SCE CE t SA t SCE t t AW HA t PWE WE t t SD HD DATA I/O DATA VALID [16, 17] Write Cycle No. 2 (WE Controlled, OE HIGH During Write) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE OE t SD t HD DATA VALID IN DATA I/O NOTE 18 t HZOE Notes 16. Data I/O is high impedance if OE = V . IH 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 18. During thi
ページ7に含まれる内容の要旨
CY7C1018DV33 Switching Waveforms (continued) [11, 17] Write Cycle No. 3 (WE Controlled, OE LOW) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE t t SD HD DATA I/O NOTE 18 DATA VALID t t LZWE HZWE Truth Table CE OE WE I/O –I/O Mode Power 0 7 H X X High-Z Power-down Standby (I ) SB L L H Data Out Read Active (I ) CC L X L Data In Write Active (I ) CC L H H High-Z Selected, Outputs Disabled Active (I ) CC Ordering Information Speed Package Operating Ordering Code Package Type (ns) Diagram Range 10
ページ8に含まれる内容の要旨
CY7C1018DV33 Package Diagram Figure 1. 32-pin (300-Mil) Molded SOJ (51-85041) PIN 1 I.D MIN. DIMENSIONS IN INCHES MAX. 0.330 0.292 0.340 LEAD COPLANARITY 0.004 MAX. 0.305 0.810 0.830 * 0.128 0.140 0.006 0.012 * 0.026 * 0.260 0.050 0.032 0.025 0.275 TYP. 0.014 MIN. 51-85041-*A 0.020 All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05465 Rev. *D Page 8 of 9 © Cypress Semiconductor Corporation, 2006. The information contained h
ページ9に含まれる内容の要旨
CY7C1018DV33 Document History Page Document Title: CY7C1018DV33, 1-Mbit (128K x 8) Static RAM Document Number: 38-05465 Orig. of REV. ECN NO. Issue Date Description of Change Change ** 201560 See ECN SWI Advance Information data sheet for C9 IPP *A 238471 See ECN RKF DC parameters modified as per EROS (Spec # 01-02165) Pb-free Offering in the Ordering Information *B 262950 See ECN RKF Added Data Retention Characteristics table Added T Spec in Switching Characteristics table power Shaded Orderi
