ページ1に含まれる内容の要旨
1M x 8 Array
1M x 8 Array
CY7C1310AV18
CY7C1312AV18
PRELIMINARY
CY7C1314AV18
18-Mb QDR™-II SRAM 2-Word Burst Architecture
Features Functional Description
• Separate independent Read and Write data ports
The CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 are
— Supports concurrent transactions
1.8V Synchronous Pipelined SRAMs, equipped with QDR-II
architecture. QDR-II architecture consists of two separate
• 167-MHz clock for high bandwidth
ports to access the memory array. The Read port has
• 2-Word Burs
ページ2に含まれる内容の要旨
256K x 36 Array 512K x 18 Array 256K x 36 Array 512K x 18 Array CY7C1310AV18 CY7C1312AV18 PRELIMINARY CY7C1314AV18 Logic Block Diagram (CY7C1312AV18) D [17:0] 18 Write Write Address A Reg Reg (18:0) Register 19 Address Register A (18:0) 19 RPS K Control CLK K Logic Gen. C DOFF Read Data Reg. CQ C CQ 36 18 V REF 18 Reg. Reg. WPS 18 Control Logic 18 BWS [1:0] Reg. Q [17:0] 18 Logic Block Diagram (CY7C1314AV18) D [35:0] 36 Write Write Address A Reg Reg (17:0) Address Register 18 Register A (17:0
ページ3に含まれる内容の要旨
CY7C1310AV18 CY7C1312AV18 PRELIMINARY CY7C1314AV18 Pin Configurations CY7C1310AV18 (2M × 8) – 11 × 15 BGA 23 89 10 11 1 45 6 7 A V /72M A NC/144M AV /36M CQ RPS SS BWS SS WPS K CQ 1 B NC NC NC A NC/288M A NC NC Q3 K BWS 0 C NC NC V AAA V NC NC D3 NC SS SS D NC D4 NC V V V V V NC NC NC SS SS SS SS SS E NC NC Q4 V V V VSS V NC D2 Q2 DDQ SS SS DDQ NC NC V V V V V NC NC NC F NC DDQ DD SS DD DDQ D5 Q5 V V V V V NC NC NC G NC DDQ DD SS DD DDQ V V V V V V V V V ZQ H DOFF REF DDQ DDQ DD SS DD DDQ DDQ
ページ4に含まれる内容の要旨
CY7C1310AV18 CY7C1312AV18 PRELIMINARY CY7C1314AV18 Pin Configurations (continued) CY7C1314AV18 (512k × 36) – 11 × 15 BGA 1 23 4 56 7 89 10 11 V /288M NC/72M NC/36M V /144M CQ A CQ SS SS WPS BWS K BWS RPS 2 1 Q27 Q18 D18 A A D17 Q17 Q8 B BWS K BWS 3 0 D27 C Q28 D19 V AA A V D16 Q7 D8 SS SS D28 D20 Q19 V V V V V Q16 D15 D7 D SS SS SS SS SS Q29 D29 Q20 V V V V V Q15 D6 Q6 E DDQ SS SS SS DDQ Q30 F Q21 D21 V V V V V D14 Q14 Q5 DDQ DD SS DD DDQ D30 G D22 Q22 V V V V V Q13 D13 D5 DDQ DD SS DD DDQ H V
ページ5に含まれる内容の要旨
CY7C1310AV18 CY7C1312AV18 PRELIMINARY CY7C1314AV18 Pin Definitions (continued) Pin Name I/O Pin Description Q Outputs- Data Output signals. These pins drive out the requested data during a Read operation. [x:0] Synchronous Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode. When the Read port is deselected, Q are automatically tri-stated. [x:0] CY7C1310AV18 − Q [7:0] CY7C1312AV18 − Q [17:0] CY7C1314AV18 − Q [35
ページ6に含まれる内容の要旨
CY7C1310AV18 CY7C1312AV18 PRELIMINARY CY7C1314AV18 Pin Definitions (continued) Pin Name I/O Pin Description V Input- Reference Voltage Input. Static input used to set the reference level for HSTL inputs REF Reference and Outputs as well as AC measurement points. V Power Supply Power supply inputs to the core of the device. DD V Ground Ground for the device. SS V Power Supply Power supply inputs for the outputs of the device. DDQ devices without the insertion of wait states in a depth Intro
ページ7に含まれる内容の要旨
CY7C1310AV18 CY7C1312AV18 PRELIMINARY CY7C1314AV18 Depth Expansion Echo Clocks The CY7C1312AV18 has a Port Select input for each port. Echo clocks are provided on the QDR-II to simplify data This allows for easy depth expansion. Both Port Selects are capture on high-speed systems. Two echo clocks are sampled on the rising edge of the Positive Input Clock only (K). generated by the QDR-II. CQ is referenced with respect to C Each port select input can deselect the specified port. and CQ is refere
ページ8に含まれる内容の要旨
CY7C1310AV18 CY7C1312AV18 PRELIMINARY CY7C1314AV18 [2, 8] Write Cycle Descriptions (CY7C1310AV18 and CY7C1312AV18) BWS BWS KK Comments 0 1 L L L-H – During the Data portion of a Write sequence : CY7C1310AV18 − both nibbles (D ) are written into the device, [7:0] CY7C1312AV18 − both bytes (D ) are written into the device. [17:0] L L – L-H During the Data portion of a Write sequence : CY7C1310AV18 − both nibbles (D ) are written into the device, [7:0] CY7C1312AV18 − both bytes (D ) are writt
ページ9に含まれる内容の要旨
CY7C1310AV18 CY7C1312AV18 PRELIMINARY CY7C1314AV18 Current into Outputs (LOW)......................................... 20 mA Maximum Ratings Static Discharge Voltage.......................................... > 2001V (Above which useful life may be impaired.) (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Current.................................................... > 200 mA Ambient Temperature with Operating Range Power Applied........
ページ10に含まれる内容の要旨
CY7C1310AV18 CY7C1312AV18 PRELIMINARY CY7C1314AV18 [16,17] Switching Characteristics Over the Operating Range Cypress Consortium 167 MHz 133 MHz Parameter Parameter Description Min. Max. Min. Max. Unit t t K Clock and C Clock Cycle Time 6.0 7.9 7.5 8.4 ns CYC KHKH t t Input Clock (K/K and C/C) HIGH 2.4 – 3.0 – ns KH KHKL t t Input Clock (K/K and C/C) LOW 2.4 – 3.0 – ns KL KLKH t t K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise (rising 2.7 – 3.38 – ns KHKH KHKH edge to rising edge) t t
ページ11に含まれる内容の要旨
CY7C1310AV18 CY7C1312AV18 PRELIMINARY CY7C1314AV18 [20] Capacitance Parameter Description Test Conditions Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 5pF IN A V = 1.8V DD C Clock Input Capacitance 6 pF CLK V = 1.5V DDQ C Output Capacitance 7 pF O AC Test Loads and Waveforms V = 0.75V REF 0.75V V REF V 0.75V REF R = 50Ω OUTPUT [12] ALL INPUT PULSES Z = 50Ω 0 OUTPUT 1.25V Device R = 50Ω L 0.75V Under Device 0.25V Test 5pF Slew Rate = 2V / ns V = 0.75V Under REF ZQ ZQ Test RQ = RQ =
ページ12に含まれる内容の要旨
CY7C1310AV18 CY7C1312AV18 PRELIMINARY CY7C1314AV18 [21,22,23] Switching Waveforms Read/Write/Deselect Sequence READ WRITE READ WRITE READ WRITE NOP WRITE NOP 12345 6 7 8 9 10 K t t t t KH KL CYC KHKH K RPS tt t SC HC WPS A0 A1 A2 A3 A4 A5 A6 A t t t t SA HA SA HA D D10 D11 D30 D31 D50 D51 D60 D61 t t t t SD HD SD HD Q Q00 Q01 Q20 Q21 Q40 Q41 t CHZ t CLZ t t t DOH DOH CQD t KHCH t KL t t CO CO C t KH t t KHKH CYC t KHCH C t CCQO t CQOH CQ t CCQO t CQOH CQ DON’T CARE UNDEFINED Notes: 21. Q00 ref
ページ13に含まれる内容の要旨
CY7C1310AV18 CY7C1312AV18 PRELIMINARY CY7C1314AV18 TDI and TDO pins as shown in TAP Controller Block Diagram. IEEE 1149.1 Serial Boundary Scan (JTAG) Upon power-up, the instruction register is loaded with the These SRAMs incorporate a serial boundary scan test access IDCODE instruction. It is also loaded with the IDCODE port (TAP) in the FBGA package. This part is fully compliant instruction if the controller is placed in a reset state as with IEEE Standard #1149.1-1900. The TAP operates using
ページ14に含まれる内容の要旨
CY7C1310AV18 CY7C1312AV18 PRELIMINARY CY7C1314AV18 is loaded into the instruction register upon power-up or The shifting of data for the SAMPLE and PRELOAD phases whenever the TAP controller is given a test logic reset state. can occur concurrently when required - that is, while data captured is shifted out, the preloaded data can be shifted in. SAMPLE Z BYPASS The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP When the BYPASS
ページ15に含まれる内容の要旨
CY7C1310AV18 CY7C1312AV18 PRELIMINARY CY7C1314AV18 [24] TAP Controller State Diagram TEST-LOGIC 1 RESET 0 1 1 1 TEST-LOGIC/ SELECT SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 0 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 0 0 PAUSE-DR PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR UPDATE-IR 1 1 0 0 Note: 24. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05497 Rev. *A Page 15 of 21 [+] Feedback
ページ16に含まれる内容の要旨
CY7C1310AV18 CY7C1312AV18 PRELIMINARY CY7C1314AV18 TAP Controller Block Diagram 0 Bypass Register Selection Selection Circuitry Circuitry 2 1 0 TDO TDI Instruction Register 29 31 30 . . 2 1 0 Identification Register 106 . . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS [9,12,25] TAP Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit V Output HIGH Voltage I = −2.0 mA 1.4 V OH1 OH V Output HIGH Voltage I = −100 µA1.6 V OH2 OH V O
ページ17に含まれる内容の要旨
CY7C1310AV18 CY7C1312AV18 PRELIMINARY CY7C1314AV18 [26, 27] TAP AC Switching Characteristics Over the Operating Range Parameter Description Min. Max. Unit t TCK Clock Cycle Time 100 ns TCYC t TCK Clock Frequency 10 MHz TF t TCK Clock HIGH 40 ns TH t TCK Clock LOW 40 ns TL Set-up Times t TMS Set-up to TCK Clock Rise 10 ns TMSS t TDI Set-up to TCK Clock Rise 10 ns TDIS t Capture Set-up to TCK Rise 10 ns CS Hold Times t TMS Hold after TCK Clock Rise 10 ns TMSH t TDI Hold after Clock Rise 10 ns TDI
ページ18に含まれる内容の要旨
CY7C1310AV18 CY7C1312AV18 PRELIMINARY CY7C1314AV18 Identification Register Definitions CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 Instruction Field 2M x 8 1M x 18 512K x 36 Description Revision Number (31:29) 000 000 000 Version number. Cypress Device ID (28:12) 11010011010000101 11010011010010101 11010011010100101 Defines the type of SRAM. Cypress JEDEC ID (11:1) 00000110100 00000110100 00000110100 Allows unique identification of SRAM vendor. ID Register Presence (0) 1 1 1 Indicates the presence
ページ19に含まれる内容の要旨
CY7C1310AV18 CY7C1312AV18 PRELIMINARY CY7C1314AV18 Boundary Scan Order (continued) Boundary Scan Order (continued) Bit # Bump ID Bit # Bump ID 30 11F 74 2D 31 11G 75 2E 32 9F 76 1E 33 10F 77 2F 34 11E 78 3F 35 10E 79 1G 36 10D 80 1F 37 9E 81 3G 38 10C 82 2G 39 11D 83 1J 40 9C 84 2J 41 9D 85 3K 42 11B 86 3J 43 11C 87 2K 44 9B 88 1K 45 10B 89 2L 46 11A 90 3L 47 Internal 91 1M 48 9A 92 1L 49 8B 93 3N 50 7C 94 3M 51 6C 95 1N 52 8A 96 2M 53 7A 97 3P 54 7B 98 2N 55 6B 99 2P 56 6A 100 1P 57 5B 101 3
ページ20に含まれる内容の要旨
CY7C1310AV18 CY7C1312AV18 PRELIMINARY CY7C1314AV18 Ordering Information Speed Package Operating (MHz) Ordering Code Name Package Type Range 167 CY7C1310AV18-167BZC BB165D 13 x 15 x 1.4 mm FBGA Commercial CY7C1312AV18-167BZC CY7C1314AV18-167BZC 133 CY7C1310AV18-133BZC BB165D 13 x 15 x 1.4 mm FBGA Commercial CY7C1312AV18-133BZC CY7C1314AV18-133BZC Package Diagram 165 FBGA 13 x 15 x 1.40 mm BB165D 51-85180-** QDR SRAMs and Quad Data Rate SRAMs comprise a new family of products developed by Cy
