ページ1に含まれる内容の要旨
CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
1K x 8 Dual-Port Static RAM
Features Functional Description
[1]
■ True dual-ported memory cells, which allow simultaneous The CY7C130/130A/CY7C131/131A/CY7C140 and CY7C141
reads of the same memory location are high speed CMOS 1K by 8 dual-port static RAMs. Two ports
are provided permitting independent access to any location in
■ 1K x 8 organization
memory. The CY7C130/130A/ CY7C131/131A can be used as
either a standalone 8-bit dual-port static
ページ2に含まれる内容の要旨
CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Pin Configurations Figure 1. Pin Diagram - DIP (Top View) CE 48 V 1 CC L R/W 47 CE L 2 R BUSY 46 R/W L R 3 BUSY INT 45 R L 4 OE 44 INT 5 R L A 0L 43 OE 6 R A 42 A 0R 1L 7 A 41 A 2L 1R 8 A 40 A 3L 2R 9 A 39 A 4L 10 3R A 5L A 11 38 4R A A 12 37 5R 6L 7C130 A A 13 7C140 36 7L 6R A 8L 14 35 A 7R A 15 A 9L 34 8R I/O 16 A 0L 33 9R I/O 1L 17 I/O 32 7R I/O 2L 18 31 I/O 6R I/O 3L 19 30 I/O 5R I/O I/O 4L 20 29 4R I/O 21 28 I/O 5L 3R I/O I/O 22 27 2R 6L
ページ3に含まれる内容の要旨
CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Pin Definitions Left Port Right Port Description CE CE Chip Enable L R R/W R/W Read/Write Enable L R OE OE Output Enable L R A –A A –A Address 0L 11/12L 0R 11/12R I/O –I/O I/O –I/O Data Bus Input/Output 0L 15/17L 0R 15/17R INT INT Interrupt Flag L R BUSY BUSY Busy Flag L R V Power CC GND Ground Selection Guide 7C130-30 7C130-35 7C130-45 7C130-55 [4] 7C131-15 7C130A-30 [4] 7C131-25 7C131-35 7C131-45 7C131-55 Parameter 7C131A-15 7C131-30 Unit 7
ページ4に含まれる内容の要旨
CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 [5] DC Input Voltage ............................................–3.5V to +7.0V Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA Exceeding maximum ratings may shorten the useful life of the Static Discharge Voltage........................................... >2001V device. User guidelines are not tested. (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch
ページ5に含まれる内容の要旨
CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 [10] Capacitance Parameter Description Test Conditions Max Unit C Input Capacitance T = 25°C, f = 1 MHz, 15 pF IN A V = 5.0V CC C Output Capacitance 10 pF OUT Figure 4. AC Test Loads and Waveforms 5V R1 893Ω R1 893Ω 5V 5V OUTPUT OUTPUT 281Ω BUSY R2 R2 OR 30 pF 5pF 347Ω 347Ω INT 30 INCLUDING INCLUDING pF JIGAND JIGAND (a) (b) SCOPE SCOPE BUSY Output Load ALL INPUT PULSES (CY7C130/CY7C131 ONLY) 3.0V Equivalent to: THÉVENIN EQUIVALENT 90% 90% 10
ページ6に含まれる内容の要旨
CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 [7, 12] Switching Characteristics Over the Operating Range 7C130-30 [4] 7C130-25 [4] 7C131-15 7C130A-30 7C131-25 7C131A-15 7C131-30 7C140-25 Parameter Description Unit 7C141-15 7C140-30 7C141-25 7C141-30 Min Max Min Max Min Max Read Cycle t Read Cycle Time 15 25 30 ns RC [13] t Address to Data Valid 15 25 30 ns AA t Data Hold from Address Change 0 00 ns OHA [13] t CE LOW to Data Valid 15 25 30 ns ACE [13] t OE LOW to Data Valid 10 15 20 ns DO
ページ7に含まれる内容の要旨
CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 [7, 12] Switching Characteristics Over the Operating Range (continued) 7C130-30 [4] 7C130-25 [4] 7C131-15 7C130A-30 7C131-25 7C131A-15 7C131-30 7C140-25 Parameter Description Unit 7C141-15 7C140-30 7C141-25 7C141-30 Min Max Min Max Min Max Busy/Interrupt Timing t BUSY LOW from Address Match 15 20 20 ns BLA [17] t BUSY HIGH from Address Mismatch 15 20 20 ns BHA t BUSY LOW from CE LOW 15 20 20 ns BLC [17] t BUSY HIGH from CE HIGH 15 20 20 ns BH
ページ8に含まれる内容の要旨
CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 [7,12] Switching Characteristics Over the Operating Range 7C130-35 7C130-45 7C130-55 7C131-35 7C131-45 7C131-55 7C140-35 7C140-45 7C140-55 Parameter Description Unit 7C141-35 7C141-45 7C141-55 Min Max Min Max Min Max Read Cycle t Read Cycle Time 35 45 55 ns RC [13] t Address to Data Valid 35 45 55 ns AA t Data Hold from Address Change 0 0 0 ns OHA [13] t CE LOW to Data Valid 35 45 55 ns ACE [13] t OE LOW to Data Valid 20 25 25 ns DOE [10, 14,
ページ9に含まれる内容の要旨
CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Switching Waveforms [20, 21] Figure 5. Read Cycle No. 1 Either Port Address Access t RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID [20, 22] Figure 6. Read Cycle No. 2 Either Port CE/OE Access CE t HZCE t ACE OE t HZOE t DOE t LZOE t LZCE DATA VALID DATA OUT t PU t PD I CC I SB [21] Figure 7. Read Cycle No. 3 Read with BUSY, Master: CY7C130 and CY7C131 t RC ADDRESS ADDRESS MATCH R t PWE R/W R t HD D VALID INR ADDRESS ADDRESS
ページ10に含まれる内容の要旨
CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Switching Waveforms (continued) [16, 23] Figure 8. Write Cycle No. 1 (OE Three-States Data I/Os—Either Port Either Port t WC ADDRESS t SCE CE t t AW HA t t SA PWE R/W t t SD HD DATA IN DATA VALID OE t HZOE HIGH IMPEDANCE D OUT [17, 24] Figure 9. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port) t WC ADDRESS t t SCE HA CE t AW t t SA PWE R/W t t SD HD DATA IN DATA VALID t LZWE t HZWE HIGH IMPEDANCE DATA OUT Notes 23. If OE is LOW du
ページ11に含まれる内容の要旨
CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Switching Waveforms (continued) Figure 10. Busy Timing Diagram No. 1 (CE Arbitration) CE Valid First: L ADDRESS L, R ADDRESS MATCH CE L t PS CE R t t BLC BHC BUSY R CE Valid First: R ADDRESS ADDRESS MATCH L,R CE R t PS CE L t t BLC BHC BUSY L Figure 11. Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First: t or t RC WC ADDRESS MATCH ADDRESS MISMATCH ADDRESS L t PS ADDRESS R t t BLA BHA BUSY R Right Address Valid First:
ページ12に含まれる内容の要旨
CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Switching Waveforms (continued) Figure 12. Busy Timing Diagram No. 3 Write with BUSY (Slave:CY7C140/CY7C141) CE t PWE R/W t t WB WH BUSY Document #: 38-06002 Rev. *E Page 12 of 19 [+] Feedback
ページ13に含まれる内容の要旨
CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Switching Waveforms (continued) Figure 13. Interrupt Timing Diagrams Left Side Sets INT R t WC ADDR WRITE 3FF L t t INS HA CE L t EINS R/W L t SA t WINS INT R Right Side Clears INT R t RC ADDR READ 3FF R t t HA INT CE R t EINR R/W R OE R t OINR INT R Right Side Sets INT L t WC ADDR R WRITE 3FE t t INS HA CE R t EINS R/W R t SA t WINS INT L Left Side Clears INT L t RC ADDR READ 3FE R t t HA INR CE L t EINR R/W L OE L t OINR INT L Document #:
ページ14に含まれる内容の要旨
CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT OUTPUT SOURCE CURRENT NORMALIZED S UPPLY CURRENT vs. AMBIENT TEMPERATURE vs. OUTPUT VOLTAGE vs. SUPPLY VOLTAGE 1.4 1.2 120 I CC 1.2 1.0 100 I CC 1.0 80 0.8 0.8 60 0.6 V = 5.0V V = 5.0V CC CC 0.6 T = 25°C V = 5.0V A IN 0.4 40 0.4 0.2 I 20 SB3 I 0.2 SB3 0 0.6 0.0 –55 25 125 0 1.0 2.0 3.0 4.0 4.0 4.5 5.0 5.5 6.0 AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V) SUPPLY VOLTAGE (V) NORMALI
ページ15に含まれる内容の要旨
CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Ordering Information Speed Package Operating Ordering Code Package Type (ns) Name Range 30 CY7C130-30PC P25 48-Pin (600 Mil) Molded DIP Commercial CY7C130A-30PI P25 48-Pin Pb-Free (600 Mil) Molded DIP Industrial 35 CY7C130-35PC P25 48-Pin (600 Mil) Molded DIP Commercial CY7C130-35PI P25 48-Pin (600 Mil) Molded DIP Industrial 45 CY7C130-45PC P25 48-Pin (600 Mil) Molded DIP Commercial CY7C130-45PI P25 48-Pin (600 Mil) Molded DIP Industrial 55 CY
ページ16に含まれる内容の要旨
CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Ordering Information (continued) Speed Package Operating Ordering Code Package Type (ns) Name Range 35 CY7C140-35PC P25 48-Pin (600 Mil) Molded DIP Commercial CY7C140-35PI P25 48-Pin (600 Mil) Molded DIP Industrial 45 CY7C140-45PC P25 48-Pin (600 Mil) Molded DIP Commercial CY7C140-45PI P25 48-Pin (600 Mil) Molded DIP Industrial 55 CY7C140-55PC P25 48-Pin (600 Mil) Molded DIP Commercial CY7C140-55PI P25 48-Pin (600 Mil) Molded DIP Industrial 15
ページ17に含まれる内容の要旨
CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Package Diagrams Figure 14. 48-Pin (600 Mil) Sidebraze DIP D26 MIL-STD-1835 D-14 Config. C 51-80044 ** Figure 15. 52-Pin Pb-Free Plastic Leaded Chip Carrier J69 MIN. DIMENSIONS IN INCHES MAX. SEATING PLANE PIN #1 ID 7 1 47 8 46 0.013 0.021 0.750 0.045 0.690 0.785 0.756 0.055 0.730 0.795 20 34 0.023 0.033 21 33 0.020 MIN. 0.750 0.090 0.756 0.130 0.165 0.785 0.200 0.795 51-85004-*A Document #: 38-06002 Rev. *E Page 17 of 19 [+] Feedback 0
ページ18に含まれる内容の要旨
CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Package Diagrams (continued) Figure 16. 48-Pin (600 Mil) Molded DIP P25 51-85020-*B Figure 17. 52-Pin Pb-Free Plastic Quad Flatpack N52 51-85042-** Document #: 38-06002 Rev. *E Page 18 of 19 [+] Feedback
ページ19に含まれる内容の要旨
CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Document History Page Document Title: CY7C130/CY7C130A/CY7C131/CY7C131A/CY7C140/CY7C141 1K x 8 Dual-Port Static RAM Document Number: 38-06002 Orig. of Submission Rev. ECN No. Description of Change Change Date ** 110169 SZV 09/29/01 Change from Spec number: 38-00027 to 38-06002 *A 122255 RBI 12/26/02 Power up requirements added to Maximum Ratings Information *B 236751 YDT See ECN Removed cross information from features section *C 325936 RUY Se
