ページ1に含まれる内容の要旨
CY7C1339G
4-Mbit (128K x 32) Pipelined Sync SRAM
[1]
Features Functional Description
• Registered inputs and outputs for pipelined operation The CY7C1339G SRAM integrates 128K x 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
• 128K × 32 common I/O architecture
counter for internal burst operation. All synchronous inputs are
• 3.3V core power supply (V )
DD gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
ページ2に含まれる内容の要旨
CY7C1339G Selection Guide 250 MHz 200 MHz 166 MHz 133 MHz Unit Maximum Access Time 2.6 2.8 3.5 4.0 ns Maximum Operating Current 325 265 240 225 mA Maximum CMOS Standby Current 40 40 40 40 mA Pin Configurations 100-Pin TQFP Pinout NC 1 80 NC DQ C DQ 2 79 B DQ C 3 78 DQ B V DDQ 4 77 V DDQ V V SSQ 5 76 SSQ DQ C 6 75 DQ B DQ BYTE C BYTE B C DQ 7 74 B DQ C 8 73 DQ B DQ C 9 72 DQ B V SSQ V 10 71 SSQ V DDQ 11 70 V DDQ DQ C 12 69 DQ B DQ DQ C 13 68 B NC 14 67 V SS V DD NC 15 66 NC 16 65 V CY7C1339G DD
ページ3に含まれる内容の要旨
CY7C1339G Pin Configurations (continued) 119-Ball BGA Pinout 1 23 4 5 6 7 A V AA A A V ADSP DDQ DDQ B NC/288M CE A A NC/9M NC/576M ADSC 2 C NC/144M A A V A A NC/1G DD DQ NC V NC V NC DQ D C SS SS B E DQ DQ V CE V DQ DQ C C SS 1 SS B B F V DQ V OE V DQ V DDQ C SS SS B DDQ G DQ DQ BW ADV BW DQ DQ C C c B B B DQ DQ V GW V DQ DQ H C C SS SS B B J V V NC V NC V V DDQ DD DD DD DDQ DQ DQ V CLK V DQ DQ K D D SS SS A A DQ DQ BW NC BW DQ DQ L D D D A A A M V DQ V V DQ V BWE DDQ D SS SS A DDQ N DQ DQ V A1
ページ4に含まれる内容の要旨
CY7C1339G Pin Definitions (continued) Name I/O Description ADV Input- Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it Synchronous automatically increments the address in a burst cycle. ADSP Input- Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A1, A0 are also loaded into the burst counter. When ADSP and ADSC are both asse
ページ5に含まれる内容の要旨
CY7C1339G signal. Consecutive single Read cycles are supported. Once to the DQs inputs. Doing so will tri-state the output drivers. As the SRAM is deselected at clock rise by the chip select and a safety precaution, DQs are automatically tri-stated whenever either ADSP or ADSC signals, its output will tri-state immedi- a Write cycle is detected, regardless of the state of OE. ately. Burst Sequences Single Write Accesses Initiated by ADSP The CY7C1339G provides a two-bit wraparound counter, fed T
ページ6に含まれる内容の要旨
CY7C1339G [2, 3, 4, 5, 6, 7] Truth Table Operation Add. Used CE CE CE ADSP ADSC ADV WRITE OE CLK DQ ZZ 1 2 3 Deselect Cycle, Power-down None H X X L X L X X X L-H Tri-State Deselect Cycle, Power-down None L L X L L X X X X L-H Tri-State Deselect Cycle, Power-down None L X H L L X X X X L-H Tri-State Deselect Cycle, Power-down None L L X L H L X X X L-H Tri-State Deselect Cycle, Power-down None L X H L H L X X X L-H Tri-State Snooze Mode, Power-down None X X X H X X X X X X Tri-State READ Cycle,
ページ7に含まれる内容の要旨
CY7C1339G [2, 8] Partial Truth Table for Read/Write Function GW BWE BW BW BW BW D C B A Read H H XXXX Read H L HHHH Write Byte A – DQ H L HHH L A Write Byte B – DQ HL H H L H B Write Bytes B, A H L H H L L Write Byte C– DQ HL HL H H C Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D– DQ H L L HHH D Write Bytes D, A H L L H H L Write Bytes D, B H L L H L H Write Bytes D, B, A H L L H L L Write Bytes D, C H L L L H H Write Bytes D, C, A H L L L
ページ8に含まれる内容の要旨
CY7C1339G DC Input Voltage ................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage.......................................... > 2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Current....................................................
ページ9に含まれる内容の要旨
CY7C1339G [9, 10] Electrical Characteristics Over the Operating Range (continued) Parameter Description Test Conditions Min. Max. Unit I Automatic CE V = Max, Device Deselected, or 4-ns cycle, 250 MHz 105 mA SB3 DD Power-down V ≤ 0.3V or V > V – 0.3V IN IN DDQ 5-ns cycle, 200 MHz 95 mA Current—CMOS Inputs f = f = 1/t MAX CYC 6-ns cycle, 166 MHz 85 mA 7.5-ns cycle, 133 MHz 75 mA I Automatic CE V = Max, Device Deselected, All Speeds 45 mA SB4 DD Power-down V ≥ V or V ≤ V , f = 0 IN IH IN IL Curr
ページ10に含まれる内容の要旨
CY7C1339G [12, 13, 14, 15, 16, 17] Switching Characteristics Over the Operating Range –250 –200 –166 –133 Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit [12] t V (Typical) to the first Access 11 1 1 ms POWER DD Clock t Clock Cycle Time 4.0 5.0 6.0 7.5 ns CYC t Clock HIGH 1.7 2.0 2.5 3.0 ns CH t Clock LOW 1.7 2.0 2.5 3.0 ns CL Output Times t Data Output Valid After CLK Rise 2.6 2.8 3.5 4.0 ns CO t Data Output Hold After CLK Rise 1.0 1.0 1.5 1.5 ns DOH [13, 14, 15] t Clock to
ページ11に含まれる内容の要旨
CY7C1339G Switching Waveforms [18] Read Cycle Timing t CYC CLK t t CH CL t t ADS ADH ADSP t t ADH ADS ADSC t t AS AH ADDRESS A1 A2 A3 Burst continued with t t WES WEH new base address GW, BWE, BW[A:D] Deselect t t CES CEH cycle CE t t ADVS ADVH ADV ADV suspends burst. OE t t OEV CO t t OEHZ t t CHZ OELZ DOH t CLZ Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Data Out (Q) High-Z Q(A1) t CO Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note: 18. On th
ページ12に含まれる内容の要旨
CY7C1339G Switching Waveforms (continued) [18, 19] Write Cycle Timing t CYC CLK t t CH CL t t ADS ADH ADSP ADSC extends burst t t ADH ADS t t ADH ADS ADSC t t AS AH ADDRESS A1 A2 A3 Byte write signals are ignored for first cycle when t t ADSP initiates burst WES WEH BWE, BW[A :D] t t WES WEH GW t t CES CEH CE t t ADVS ADVH ADV ADV suspends burst OE t t DS DH Data In (D) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) High-Z D(A1) t OEHZ Data Out (Q) BURST READ Single WRI
ページ13に含まれる内容の要旨
CY7C1339G Switching Waveforms (continued) [18, 20, 21] Read/Write Cycle Timing t CYC CLK t t CL CH t t ADS ADH ADSP ADSC t t AH AS A1 A2 A3 A4 A5 A6 ADDRESS t t WES WEH BWE, BW[A:D] t t CES CEH CE ADV OE t t t CO DS DH t OELZ Data In (D) High-Z D(A3) D(A5) D(A6) t t OEHZ CLZ Data Out (Q) High-Z Q(A1) Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) Back-to-Back READs Single WRITE BURST READ Back-to-Back WRITEs DON’T CARE UNDEFINED Notes: 20. The data bus (Q) remains in high-Z following a WRITE cycle, unles
ページ14に含まれる内容の要旨
CY7C1339G Switching Waveforms (continued) [22, 23] ZZ Mode Timing CLK t t ZZ ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI ALL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Notes: 22. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 23. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05520 Rev. *F Page 14 of 18 [+] Feedback
ページ15に含まれる内容の要旨
CY7C1339G Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed Package Operating (MHz) Ordering Code Diagram Package Type Range 133 CY7C1339G-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1339G-133BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1339G-133BGXC 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
ページ16に含まれる内容の要旨
CY7C1339G Package Diagrams 100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050) 16.00±0.20 1.40±0.05 14.00±0.10 100 81 1 80 0.30±0.08 0.65 12°±1° SEE DETAIL A TYP. (8X) 30 51 31 50 0.20 MAX. 1.60 MAX. R 0.08 MIN. 0° MIN. 0.20 MAX. SEATING PLANE STAND-OFF 0.05 MIN. NOTE: 0.25 0.15 MAX. 1. JEDEC STD REF MS-026 GAUGE PLANE 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE R 0.08 MIN. BODY LENGTH DIMENSIONS ARE MAX PLAS
ページ17に含まれる内容の要旨
CY7C1339G Package Diagrams (continued) 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115) Ø0.05 M C Ø0.25MCAB A1 CORNER Ø0.75±0.15(119X) Ø1.00(3X) REF. 16 237 4 5 7 65 43 21 A A B B C C D D E E F F G G H H J J K K L L M M N N P P R R T T U U 1.27 0.70 REF. A 3.81 12.00 7.62 B 14.00±0.20 0.15(4X) 30° TYP. 51-85115-*B SEATING PLANE C All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05520 Rev. *F Page 17 of 18 © Cypress Semiconduct
ページ18に含まれる内容の要旨
CY7C1339G Document History Page Document Title: CY7C1339G 4-Mbit (128K x 32) Pipelined Sync SRAM Document Number: 38-05520 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 224368 See ECN RKF New data sheet *A 288909 See ECN VBL In Ordering Info section, Changed TQFP to PB-free TQFP Added PB-free BG package *B 332895 See ECN SYT Modified Address Expansion balls in the pinouts for 100 TQFP and 119 BGA Package as per JEDEC standards and updated the Pin Definitions accordingly Modi
