ページ1に含まれる内容の要旨
CY7C65113C
USB Hub with Microcontroller
USB Hub with Microcontroller
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-08002 Rev. *D Revised March 6, 2006
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ページ2に含まれる内容の要旨
CY7C65113C TABLE OF CONTENTS 1.0 FEATURES ......................................................................................................................................5 2.0 FUNCTIONAL OVERVIEW .............................................................................................................6 3.0 PIN CONFIGURATIONS .................................................................................................................8 4.0 PRODUCT SUMMARY TABLES ................
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CY7C65113C 16.0 USB HUB .....................................................................................................................................29 16.1 Connecting/Disconnecting a USB Device ..............................................................................29 16.2 Enabling/Disabling a USB Device ..........................................................................................30 16.3 Hub Downstream Ports Status and Control ...................................
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CY7C65113C Figure 16-5. Hub Ports Force Low Register .........................................................................................31 Figure 16-6. Hub Ports SE0 Status Register .......................................................................................31 Figure 16-7. Hub Ports Data Register ..................................................................................................32 Figure 16-8. Hub Ports Suspend Register ......................................
ページ5に含まれる内容の要旨
CY7C65113C 1.0 Features • Full Speed USB hub with an integrated microcontroller • 8-bit USB optimized microcontroller — Harvard architecture — 6-MHz external clock source — 12-MHz internal CPU clock — 48-MHz internal hub clock • Internal memory — 256 bytes of RAM — 8 KB of PROM 2 • Integrated Master/Slave I C-compatible Controller (100 kHz) enabled through General-purpose I/O (GPIO) pins • I/O ports — Two GPIO ports (Port 0 to 2) capable of sinking 7 mA per pin (typical) — Higher current drive
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CY7C65113C 2.0 Functional Overview The CY7C65113C device is a one-time programmable 8-bit microcontroller with a built-in 12-Mbps USB hub that supports up to four downstream ports. The microcontroller instruction set has been optimized specifically for USB operations, although the microcontrollers can be used for a variety of non-USB embedded applications. GPIO The CY7C65113C has 11 GPIO pins (P0[7:0], P1[2:0]), both rated at 7 mA per pin (typical) sink current. Multiple GPIO pins can be conne
ページ7に含まれる内容の要旨
CY7C65113C Logic Block Diagram 6-MHz crystal USB D+[0] Upstream USB Port D–[0] Transceiver Downstream USB Ports PLL USB D+[1] D–[1] Transceiver 48 MHz Clock 12-MHz Divider USB D+[2] 8-bit D–[2] Transceiver CPU 12 MHz Repeater USB SIE USB PROM D+[3] D–[3] Transceiver 8 KB RAM Interrupt USB D+[4] D–[4] 256 byte Controller Transceiver 6 MHz Power management under firmware 12-bit control using GPIO pins Timer P0[0] GPIO PORT 0 P0[7] Watchdog P1[0] Timer GPIO PORT 1 P1[2] Power-on Reset 2 I C com
ページ8に含まれる内容の要旨
CY7C65113C 3.0 Pin Configurations Top View CY7C65113C 28-pin SOIC XTALOUT 1 28 V CC 2 27 P1[1] XTALIN 26 3 P1[0] V REF 4 P1[2] GND 25 D–[3] D+[0] 5 24 D+[3] D–[0] 6 23 D–[4] D+[1] 7 22 D+[4] D–[1] 8 21 D+[2] 9 20 GND D–[2] 10 19 V PP P0[7] 11 18 P0[0] P0[5] 12 17 P0[2] P0[3] 13 16 P0[4] P0[1] 14 15 P0[6] 4.0 Product Summary Tables 4.1 Pin Assignments Table 4-1. Pin Assignments Name I/O 28-pin Description D+[0], D–[0] I/O 5, 6 Upstream port, USB differential data. D+[1], D–[1] I/O 7, 8 Downst
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CY7C65113C 4.2 I/O Register Summary I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads data from the selected port into the accumulator. IOWR performs the reverse; it writes data from the accumulator to the selected port. Indexed I/O Write (IOWX) adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to the specified port. Specifying address 0 (e.g., IOWX 0h) means the I/O regist
ページ10に含まれる内容の要旨
CY7C65113C Table 4-2. I/O Register Summary (continued) Register Name I/O Address Read/Write Function Page Hub Port Control (Ports [4:1]) 0x4B R/W Hub Downstream Ports Control (Ports [4:1]) 31 Hub Port Suspend 0x4D R/W Hub Downstream Port Suspend Control 32 Hub Port Resume Status 0x4E R Hub Downstream Ports Resume Status 33 Hub Ports SE0 Status 0x4F R Hub Downstream Ports SE0 Status 31 Hub Ports Data 0x50 R Hub Downstream Ports Differential Data 32 Hub Downstream Force Low 0x51 R/W Hub Downst
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CY7C65113C Table 4-3. Instruction Set Summary (continued) MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles XPAGE 1F 4 RET 3F 8 MOV A,X 40 4 DI 70 4 MOV X,A 41 4 EI 72 4 MOV PSP,A 60 4 RETI 73 8 CALL addr 50-5F 10 JC addr C0-CF 5 (or 4) JMP addr 80-8F 5 JNC addr D0-DF 5 (or 4) CALL addr 90-9F 10 JACC addr E0-EF 7 JZ addr A0-AF 5 (or 4) INDEX addr F0-FF 14 JNZ addr B0-BF 5 (or 4) 5.0 Programming Model 5.1 14-bit Program Counter The 14-bit Program Counter (PC) allows access to up t
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CY7C65113C 5.1.1 Program Memory Organization after reset Address 14-bit PC 0x0000 Program execution begins here after a reset 0x0002 USB Bus Reset interrupt vector 0x0004 128-µs timer interrupt vector 0x0006 1.024-ms timer interrupt vector 0x0008 USB address A endpoint 0 interrupt vector 0x000A USB address A endpoint 1 interrupt vector 0x000C USB address A endpoint 2 interrupt vector 0x000E USB address B endpoint 0 interrupt vector 0x0010 USB address B endpoint 1 interrupt vector 0x0012 Hub
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CY7C65113C 5.2 8-bit Accumulator (A) The accumulator is the general-purpose register for the microcontroller. 5.3 8-bit Temporary Register (X) The “X” register is available to the firmware for temporary storage of intermediate results. The microcontroller can perform indexed operations based on the value in X. Refer to Section 5.6.3 for additional information. 5.4 8-bit Program Stack Pointer (PSP) During a reset, the Program Stack Pointer (PSP) is set to 0x00 and “grows” upward from this addr
ページ14に含まれる内容の要旨
CY7C65113C 5.5 8-bit Data Stack Pointer (DSP) The Data Stack Pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH instruction pre-decrements the DSP, then writes data to the memory location addressed by the DSP. A POP instruction reads data from the memory location addressed by the DSP, then post-increments the DSP. During a reset, the DSP is reset to 0x00. A PUSH instruction when DSP equals 0x00 writes data at the top of the data RAM (address
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CY7C65113C 6.0 Clocking XTALOUT (pin 1) XTALIN To Internal PLL (pin 2) 30 pF 30 pF Figure 6-1. Clock Oscillator On-Chip Circuit The XTALIN and XTALOUT are the clock pins to the microcontroller. The user can connect an external oscillator or a crystal to these pins. When using an external crystal, keep PCB traces between the chip leads and crystal as short as possible (less than 2 cm). A 6-MHz fundamental frequency parallel resonant crystal can be connected to these pins to provide a refere
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CY7C65113C 7.2 Watchdog Reset The WDR occurs when the internal Watchdog Timer rolls over. Writing any value to the write-only Watchdog Reset Clear Register (Figure 7-1) clears the timer. The timer rolls over and WDR occurs if it is not cleared within t of the last clear (see Section WATCH 23.0 for the value of t ). Bit 6 of the Processor Status and Control Register (Figure 13-1) is set to record this event (the WATCH register contents are set to 010X0001 by the WDR). A Watchdog Timer Reset las
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CY7C65113C 9.0 General-purpose I/O Ports V CC GPIO mode CFG 2-bits OE Q1 Q2 Data Internal Out Data Bus Latch 14 kΩ GPIO Port Write PIN Q3* Data Port Read In Latch Reg_Bit STRB (Latch is Transparent) Data Interrupt Latch Interrupt Enable Interrupt *Port 0,1: Low I Controller sink Figure 9-1. Block Diagram of a GPIO Pin There are 11 GPIO pins (P0[7:0] and P1[2:0]) for the hardware interface. Each port can be configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS ou
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CY7C65113C 9.1 GPIO Configuration Port Every GPIO port can be programmed as inputs with internal pull-ups, outputs LOW or HIGH, or Hi-Z (floating, the pin is not driven internally). In addition, the interrupt polarity for each port can be programmed. The Port Configuration bits (Figure 9-4) and the Interrupt Enable bit (Figure 9-5 through Figure 9-6) determine the interrupt polarity of the port pins . GPIO Configuration Address 0x08 Bit # 7 6 5 432 10 Bit Name Reserved Reserved Reserved Reser
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CY7C65113C Table 9-1. GPIO Port Output Control Truth Table and Interrupt Polarity Port Config Bit 1 Port Config Bit 0 Data Register Output Drive Strength Interrupt Enable Bit Interrupt Polarity 1 1 0 Output LOW 0 Disabled 1 Resistive 1 – (Falling Edge) 1 0 0 Output LOW 0 Disabled 1 Output HIGH 1 Disabled 0 1 0 Output LOW 0 Disabled 1 Hi-Z 1 – (Falling Edge) 0 0 0 Output LOW 0 Disabled 1 Hi-Z 1 + (Rising Edge) Q1, Q2, and Q3 discussed below are the transistors referenced in Figure 9-1. The a
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CY7C65113C Timer LSB Address 0x24 Bit # 765 43 210 Bit Name Timer Bit 7 TimerBit 6 Timer Bit 5 Timer Bit 4 Timer Bit 3 Timer Bit 2 Timer Bit 1 Timer Bit 0 Read/Write R RRR RR RR Reset 000 00 000 Figure 10-1. Timer LSB Register Bit [7:0]: Timer lower eight bits. Timer MSB Address 0x25 Bit # 765 43 210 Bit Name Reserved Reserved Reserved Reserved Timer Bit 11 Timer Bit 10 Timer Bit 9 Timer Bit 8 Read/Write – – – – R R R R Reset 000 00 000 Figure 10-2. Timer MSB Register Bit [3:0]: Timer higher
