ページ1に含まれる内容の要旨
Ultra37000 CPLD Family
5V, 3.3V, ISR™ High-Performance CPLDs
Features General Description
• In-System Reprogrammable™ (ISR™) CMOS CPLDs The Ultra37000™ family of CMOS CPLDs provides a range of
high-density programmable logic solutions with unparalleled
— JTAG interface for reconfigurability
system performance. The Ultra37000 family is designed to
— Design changes do not cause pinout changes
bring the flexibility, ease of use, and performance of the 22V10
to high-density CPLDs. The architecture i
ページ2に含まれる内容の要旨
Ultra37000 CPLD Family Selection Guide 5.0V Selection Guide General Information Device Macrocells Dedicated Inputs I/O Pins Speed (t )Speed (f ) PD MAX CY37032 32 5 32 6 200 CY37064 64 5 32/64 6 200 CY37128 128 5 64/128 6.5 167 CY37192 192 5 120 7.5 154 CY37256 256 5 128/160/192 7.5 154 CY37384 384 5 160/192 10 118 CY37512 512 5 160/192/264 10 118 Speed Bins Device 200 167 154 143 125 100 83 66 CY37032 X X X CY37064 X X X CY37128 X X X CY37192 X X X CY37256 X X X CY37384 X X CY37512 X X X Device
ページ3に含まれる内容の要旨
Ultra37000 CPLD Family Speed Bins Device 200 167 154 143 125 100 83 66 CY37032V X X CY37064V X X CY37128V X X CY37192V XX CY37256V XX CY37384V XX CY37512V XX Device-Package Offering and I/O Count Device CY37032V 37 37 CY37064V 37 37 37 69 69 CY37128V 69 69 85 133 CY37192V 125 CY37256V 133 133 165 197 197 CY37384V 165 197 CY37512V 165 165 197 269 269 Logic Block Architecture Overview of Ultra37000 Family The logic block is the basic building block of the Ultra37000 Programmable Interconnect Mat
ページ4に含まれる内容の要旨
Ultra37000 CPLD Family 3 2 2 0 −16 I/O MACRO- CELL CELL PRODUCT 0 0 TERMS 7 0 −16 MACRO- to cells CELL 2, 4, 6 8, 10, 12 PRODUCT 1 TERMS FROM PIM 36 80 72 x 87 PRODUCT PRODUCT TERM TERM ARRAY ALLOCATOR MACRO- I/O 0 −16 CELL CELL PRODUCT 14 14 TERMS MACRO- 0 −16 CELL TO PRODUCT 15 PIM TERMS 16 8 Figure 1. Logic Block with 50% Buried Macrocells Low-Power Option variable fashion. The software automatically takes advantage of this capability—the user does not have to intervene. Each logic block can
ページ5に含まれる内容の要旨
Ultra37000 CPLD Family The buried macrocell also supports input register capability. Bus Hold Capabilities on all I/Os The buried macrocell can be configured to act as an input Bus-hold, which is an improved version of the popular internal register (D-type or latch) whose input comes from the I/O pin pull-up resistor, is a weak latch connected to the pin that does associated with the neighboring macrocell. The output of all not degrade the device’s performance. As a latch, bus-hold buried macroc
ページ6に含まれる内容の要旨
Ultra37000 CPLD Family INPUT PIN 0 1 O TO PIM 2 D D 3 0 Q Q FROM CLOCK 1 O POLARITY MUXES 2 C12 C13 3 C10 C11 D Q LE Figure 3. Input Macrocell 0 TO CLOCK MUX ON O ALL INPUT MACROCELLS 1 INPUT/CLOCK PIN C12 0 O 1 TO CLOCK MUX IN EACH LOGIC BLOCK 0 C13, C14, C15 OR C16 1 O TO PIM 2 CLOCK POLARITY MUX D D 3 ONE PER LOGIC BLOCK 0 Q Q FROM CLOCK FOR EACH CLOCK INPUT 1 O POLARITY INPUT 2 C10C11 CLOCK PINS 3 C8 C9 D Q LE Figure 4. Input/Clock Macrocell Clocking Timing Model Each I/O and buried macroc
ページ7に含まれる内容の要旨
Ultra37000 CPLD Family resources for pinout flexibility, and a simple timing model for COMBINATORIAL SIGNAL consistent system performance. t = 6.5 ns PD INPUT OUTPUT Development Software Support Warp REGISTERED SIGNAL Warp is a state-of-the-art compiler and complete CPLD design t = 3.5 ns S t = 4.5 ns CO D,T,L O tool. For design entry, Warp provides an IEEE-STD-1076/1164 INPUT VHDL text editor, an IEEE-STD-1364 Verilog text editor, and a OUTPUT graphical finite state machine editor. It provides
ページ8に含まれる内容の要旨
Ultra37000 CPLD Family The third programming option for Ultra37000 devices is to The fourth method for programming Ultra37000 devices is to utilize the embedded controller or processor that already use the same programmer that is currently being used to exists in the system. The Ultra37000 ISR software assists in program FLASH370i devices. this method by converting the device JEDEC maps into the For all pinout, electrical, and timing requirements, refer to ISR serial stream that contains the ISR
ページ9に含まれる内容の要旨
Ultra37000 CPLD Family Logic Block Diagrams CY37032/CY37032V Clock/ Input Input TDI JTAG Tap TCK TDO Controller 4 1 TMS JTAG EN 4 4 36 36 LOGIC LOGIC 16 I/Os 16 I/Os BLOCK BLOCK 16 PIM 16 I/O −I/O I/O −I/O 16 31 0 15 A B 16 16 Clock/ CY37064/CY37064V Input Input 4 1 4 4 36 36 LOGIC LOGIC 16 I/Os 16 I/Os I/O -I/O BLOCK BLOCK I/O -I/O 0 15 16 16 48 63 A D PIM 36 36 16 I/Os 16 I/Os LOGIC LOGIC I/O -I/O BLOCK 16 BLOCK I/O -I/O 32 47 16 31 16 B C 32 32 TDI JTAG Tap TCK TDO Controller TMS Document #:
ページ10に含まれる内容の要旨
Ultra37000 CPLD Family Logic Block Diagrams (continued) TDI JTAG Tap CY37128/CY37128V CLOCK TCK TDO INPUTS INPUTS Controller TMS 1 4 INPUT/CLOCK JTAG INPUT EN MACROCELL MACROCELLS 4 4 16 I/Os LOGIC LOGIC 16 I/Os I/O –I/O BLOCK 36 36 BLOCK 0 15 I/O –I/O 112 127 A H PIM 16 16 LOGIC LOGIC 16 I/Os 16 I/Os BLOCK 36 36 BLOCK I/O –I/O I/O –I/O 16 31 96 111 B G 16 16 16 I/Os 16 I/Os LOGIC LOGIC BLOCK 36 36 BLOCK I/O –I/O I/O –I/O 32 47 80 95 C F 16 16 16 I/Os LOGIC LOGIC 16 I/Os BLOCK 36 36 BLOCK I/O –
ページ11に含まれる内容の要旨
Ultra37000 CPLD Family Logic Block Diagrams (continued) Clock/ Input Input CY37256/CY37256V 4 1 4 4 36 36 LOGIC LOGIC 12 I/Os 12 I/Os BLOCK BLOCK 16 16 I/O −I/O I/O −I/O 180 191 0 11 A P 36 36 12 I/Os 12 I/Os LOGIC LOGIC BLOCK 16 BLOCK I/O −I/O I/O −I/O 16 12 23 168 179 B O 36 36 12 I/Os 12 I/Os LOGIC LOGIC BLOCK BLOCK I/O −I/O 16 I/O −I/O 16 24 35 156 167 C N 36 36 12 I/Os 12 I/Os LOGIC LOGIC I/O −I/O BLOCK BLOCK I/O −I/O 16 36 47 16 144 155 D M 36 PIM 36 12 I/Os 12 I/Os LOGIC LOGIC I/O −I/O B
ページ12に含まれる内容の要旨
Ultra37000 CPLD Family Logic Block Diagrams (continued) Clock/ CY37384/CY37384V Input Input 4 1 4 4 36 36 LOGIC LOGIC 12 I/Os BLOCK BLOCK 16 16 I/O −I/O 0 11 AA BL 36 36 12 I/Os 12 I/Os LOGIC LOGIC BLOCK 16 BLOCK I/O −I/O 16 I/O −I/O 168 191 12 23 AB BK 36 36 12 I/Os 12 I/Os LOGIC LOGIC BLOCK 16 BLOCK I/O −I/O I/O −I/O 16 24 35 156 179 AC BJ 36 36 12 I/Os LOGIC LOGIC BLOCK BLOCK I/O −I/O 16 16 144 167 AD BI 36 36 PIM 12 I/Os LOGIC LOGIC BLOCK 16 BLOCK I/O −I/O 16 36 47 AE BH 36 36 12 I/Os LOGIC
ページ13に含まれる内容の要旨
Ultra37000 CPLD Family Logic Block Diagrams (continued) CY37512/CY37512V Input Clock/ Input 4 1 4 4 36 36 LOGIC LOGIC 12 I/Os BLOCK BLOCK 16 16 I/O −I/O 0 11 AA BP 36 36 12 I/Os 12 I/Os LOGIC LOGIC BLOCK 16 BLOCK I/O −I/O I/O −I/O 16 252 263 12 23 AB BO 36 36 12 I/Os 12 I/Os LOGIC LOGIC BLOCK BLOCK I/O −I/O 16 I/O −I/O 16 24 35 240 251 AC BN 36 36 12 I/Os LOGIC LOGIC BLOCK BLOCK I/O −I/O 16 16 228 239 AD BM 36 36 LOGIC LOGIC 12 I/Os BLOCK BLOCK 16 I/O −I/O 16 36 47 AE BL 36 36 12 I/Os LOGIC LOGI
ページ14に含まれる内容の要旨
Ultra37000 CPLD Family DC Voltage Applied to Outputs 5.0V Device Characteristics in High-Z State................................................–0.5V to +7.0V Maximum Ratings DC Input Voltage ............................................–0.5V to +7.0V (Above which the useful life may be impaired. For user guide- DC Program Voltage............................................. 4.5 to 5.5V lines, not tested.) Current into Outputs .................................................... 16 mA Storage Tem
ページ15に含まれる内容の要旨
Ultra37000 CPLD Family [5] Inductance 44-Lead 44-Lead 44-Lead 84-Lead 84-Lead 100-Lead 160-Lead 208-Lead Parameter Description Test Conditions TQFP PLCC CLCC PLCC CLCC TQFP TQFP PQFP Unit L Maximum Pin V = 5.0V 25 28 5 8 9 11 nH IN Inductance at f = 1 MHz [5] Capacitance Parameter Description Test Conditions Max. Unit C Input/Output Capacitance V = 5.0V at f = 1 MHz at T = 25°C 10 pF I/O IN A C Clock Signal Capacitance V = 5.0V at f = 1 MHz at T = 25°C 12 pF CLK IN A [9] C Dual-Function Pins V =
ページ16に含まれる内容の要旨
Ultra37000 CPLD Family [5] Inductance 44- 44- 44- 84- 84- 100- 160- 208- Lead Lead Lead Lead Lead Lead Lead Lead Parameter Description Test Conditions TQFP PLCC CLCC PLCC CLCC TQFP TQFP PQFP Unit L Maximum Pin V = 3.3V 2 528589 11 nH IN Inductance at f = 1 MHz [5] Capacitance Parameter Description Test Conditions Max. Unit C Input/Output Capacitance V = 3.3V at f = 1 MHz at T = 25°C 8 pF I/O IN A C Clock Signal Capacitance V = 3.3V at f = 1 MHz at T = 25°C 12 pF CLK IN A [9] C Dual Functional
ページ17に含まれる内容の要旨
Ultra37000 CPLD Family [11] Parameter V Output Waveform—Measurement Level X t 1.5V ER(–) V OH 0.5V V X t 2.6V ER(+) V X 0.5V V OL t 1.5V EA(+) V 0.5V OH V X t V EA(–) the V X 0.5V V OL (d) Test Waveforms [12] Switching Characteristics Over the Operating Range Parameter Description Unit Combinatorial Mode Parameters [13, 14, 15] t Input to Combinatorial Output ns PD [13, 14, 15] t Input to Output Through Transparent Input or Output Latch ns PDL [13, 14, 15] t Input to Output Through Transparent I
ページ18に含まれる内容の要旨
Ultra37000 CPLD Family [12] Switching Characteristics Over the Operating Range (continued) Parameter Description Unit Product Term Clocking Parameters [13, 14, 15] t Product Term Clock or Latch Enable (PTCLK) to Output ns COPT t Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK) ns SPT t Register or Latch Data Hold Time ns HPT [13] t Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or ns ISPT Latch Enable (PTCLK) t Buried Register Used
ページ19に含まれる内容の要旨
Ultra37000 CPLD Family [12] Switching Characteristics Over the Operating Range 200 MHz 167 MHz 154 MHz 143 MHz 125 MHz 100 MHz 83 MHz 66 MHz Parameter Unit Combinatorial Mode Parameters [13, 14, 15] t 6 6.5 7.5 8.5 10 12 15 20 ns PD [13, 14, 15] t 11 12.5 14.5 16 16.5 17 19 22 ns PDL [13, 14, 15] t 12 13.5 15.5 17 17.5 18 20 24 ns PDLL [13, 14, 15] t 8 8.5 11 13 14 16 19 24 ns EA [11, 13] t 8 8.5 11 13 14 16 19 24 ns ER Input Register Parameters t 2.5 2.5 2.5 2.5 3 3 4 5 ns WL t 2.5 2.5 2.5 2.5
ページ20に含まれる内容の要旨
Ultra37000 CPLD Family [12] Switching Characteristics Over the Operating Range (continued) 200 MHz 167 MHz 154 MHz 143 MHz 125 MHz 100 MHz 83 MHz 66 MHz Parameter Unit [13, 14, 15] t 12 13 13 14 15 18 21 26 ns RO t 8 8 8 8 10 12 15 20 ns PW [13] t 10 10 10 10 12 14 17 22 ns PR [13, 14, 15] t 12 13 13 14 15 18 21 26 ns PO User Option Parameters t 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns LP t 33 3 3 3 3 3 3ns SLEW [19] t 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 ns 3.3IO JTAG Timing Parameters t 0 00 0 00 0 0 ns
