ページ1に含まれる内容の要旨
®
CY62157E MoBL
8-Mbit (512K x 16) Static RAM
also has an automatic power-down feature that significantly
Features
reduces power consumption when addresses are not toggling.
• Very high speed: 45 ns The device can also be put into standby mode when
deselected (CE HIGH or CE LOW or both BHE and BLE are
1 2
• Wide voltage range: 4.5V–5.5V
HIGH). The input/output pins (IO through IO ) are placed in
0 15
• Ultra-low standby power
a high-impedance state when: deselected (CE HIGH or CE
1 2
LOW), ou
ページ2に含まれる内容の要旨
® CY62157E MoBL [2, 3] Pin Configuration TSOP II VFBGA Top View Top View 4 1 2 3 5 6 A A 1 44 4 5 A A 2 43 6 3 A A A CE OE A BLE 2 A 3 0 1 2 A 42 7 2 A 4 OE 1 41 A 5 40 BHE 0 IO BHE A A CE IO B 3 4 0 8 1 6 39 CE BLE IO 7 38 IO 0 15 IO IO A A IO IO C 5 6 9 10 1 2 IO 8 37 IO 1 14 IO 9 36 IO 2 13 A Vcc V IO IO A D IO 10 IO SS 7 35 11 17 3 3 12 V 11 34 V CC SS V 12 SS 33 V V IO NC A Vss CC IO E CC 16 12 4 IO 13 32 IO 4 11 IO 14 IO 5 31 10 F IO A A IO IO IO IO 14 15 IO 14 13 5 6 6 15 30 9 IO 16 29
ページ3に含まれる内容の要旨
® CY62157E MoBL [6, 7] DC Input Voltage ........................................–0.5V to 6.0V Maximum Ratings Output Current into Outputs (LOW) ............................ 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage .......................................... > 2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature ................................–65°C to + 150°C Latch-Up Current ............................................
ページ4に含まれる内容の要旨
® CY62157E MoBL [9] Thermal Resistance Parameter Description Test Conditions TSOP II VFBGA Unit Θ Thermal Resistance Still Air, soldered on a 3 × 4.5 inch, 77 72 °C/W JA (Junction to Ambient) two-layer printed circuit board Θ Thermal Resistance 13 8.86 °C/W JC (Junction to Case) AC Test Loads and Waveforms R1 ALL INPUT PULSES V CC 3V 90% OUTPUT 90% 10% 10% GND R2 30 pF Rise Time = 1 V/ns Fall Time = 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THEVENIN EQUIVALENT R TH OUTPUT V Parameters Valu
ページ5に含まれる内容の要旨
® CY62157E MoBL [12] Switching Characteristics Over the Operating Range 45 ns 55 ns Parameter Description Min Max Min Max Unit Read Cycle 45 55 t Read Cycle Time ns RC 45 55 t Address to Data Valid ns AA t Data Hold from Address Change 10 10 ns OHA t CE LOW and CE HIGH to Data Valid 45 55 ns ACE 1 2 t OE LOW to Data Valid 22 25 ns DOE [13] t OE LOW to LOW Z 5 5 ns LZOE [13, 14] t OE HIGH to High Z 18 20 ns HZOE [13] t CE LOW and CE HIGH to Low Z 10 10 ns LZCE 1 2 [13, 14] t CE HIGH and CE LO
ページ6に含まれる内容の要旨
® CY62157E MoBL Switching Waveforms [16, 17] Read Cycle 1 (Address Transition Controlled) t RC ADDRESS t AA t OHA PREVIOUS DATA VALID DATA VALID DATA OUT [17, 18] Read Cycle 2 (OE Controlled) ADDRESS t CE RC 1 t PD t HZCE CE 2 t ACE BHE/BLE t DBE t HZBE t LZBE OE t HZOE t DOE t HIGH LZOE HIGH IMPEDANCE IMPEDANCE DATA OUT DATA VALID t LZCE t I V CC PU CC 50% 50% SUPPLY I SB CURRENT Notes: 16. The device is continuously selected. OE, CE = V , BHE and/or BLE = V , and CE = V . 1 IL IL 2 IH 17.
ページ7に含まれる内容の要旨
® CY62157E MoBL Switching Waveforms (continued) [15, 19, 20, 21] Write Cycle 1 (WE Controlled) t WC ADDRESS t SCE CE 1 CE 2 t t AW HA t t SA PWE WE t BW BHE/BLE OE t t SD HD VALID DATA IO See Note 21 DATA t HZOE [15, 19, 20, 21] Write Cycle 2 (CE or CE Controlled) 1 2 t WC ADDRESS t SCE CE 1 CE 2 t SA t t AW HA t PWE WE t BHE/BLE BW OE t t SD HD VALID DATA See Note 21 DATA IO t HZOE Notes: 19. Data IO is high impedance if OE = V . IH 20. If CE goes HIGH and CE goes LOW simultaneously with WE
ページ8に含まれる内容の要旨
® CY62157E MoBL Switching Waveforms (continued) [20, 21] Write Cycle 3 (WE Controlled, OE LOW) t WC ADDRESS t SCE CE 1 CE 2 t BHE/BLE BW t t AW HA t t SA PWE WE t t SD HD DATA IO See Note 21 VALID DATA t t LZWE HZWE [20, 21] Write Cycle 4 (BHE/BLE Controlled, OE LOW) t WC ADDRESS CE 1 CE 2 t SCE t t AW HA t BW BHE/BLE t SA t PWE WE t t SD HD See Note 21 DATA IO VALID DATA Document #: 38-05695 Rev. *C Page 8 of 12 [+] Feedback
ページ9に含まれる内容の要旨
® CY62157E MoBL Truth Table CE CE WE OE BHE BLE Inputs/Outputs Mode Power 1 2 H X X X X X High Z Deselect/Power-Down Standby (I ) SB X L X X X X High Z Deselect/Power-Down Standby (I ) SB X X X X H H High Z Deselect/Power-Down Standby (I ) SB L H H L L L Data Out (IO –IO ) Read Active (I ) 0 15 CC L H H L H L Data Out (IO –IO ); Read Active (I ) 0 7 CC High Z (IO –IO ) 8 15 L H H L L H High Z (IO –IO ); Read Active (I ) 0 7 CC Data Out (IO –IO ) 8 15 L H H H L H High Z Output Disabled Active
ページ10に含まれる内容の要旨
® CY62157E MoBL Package Diagrams 44-pin TSOP II (51-85087) 51-85087-*A Document #: 38-05695 Rev. *C Page 10 of 12 [+] Feedback
ページ11に含まれる内容の要旨
® CY62157E MoBL Package Diagrams (continued) 48-ball VFBGA (6 x 8 x 1 mm) (51-85150) BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 1 2346 5 65 4 3 2 1 A A B B C C D D E E F F G G H H 1.875 A A 0.75 B 6.00±0.10 3.75 B 6.00±0.10 0.15(4X) 51-85150-*D SEATING PLANE C MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respec
ページ12に含まれる内容の要旨
® CY62157E MoBL Document History Page ® Document Title: CY62157E MoBL , 8-Mbit (512K x 16) Static RAM Document Number: 38-05695 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 291273 See ECN PCI New data sheet *A 457689 See ECN NXR Added Automotive Product Removed Industrial Product Removed 35 ns and 45 ns speed bins Removed “L” bin Updated AC Test Loads table Corrected t in Data Retention Characteristics from 100 µs to t ns R RC Updated the Ordering Information and replaced
