ページ1に含まれる内容の要旨
CY7C68053
MoBL-USB™ FX2LP18 USB Microcontroller
1.0 CY7C68053 Features
• USB 2.0 – USB-IF High-Speed and Full-Speed Compliant • Integrated, industry standard enhanced 8051
(TID# 40000188)
— 48 MHz, 24 MHz, or 12 MHz CPU operation
• Single-chip integrated USB 2.0 transceiver, smart SIE, and
— Four clocks per instruction cycle
enhanced 8051 microprocessor
— Three counter/timers
• Ideal for mobile applications (cell phone, smart phones,
— Expanded interrupt system
PDAs, MP3 players)
— Two data po
ページ2に含まれる内容の要旨
CY7C68053 Cypress Semiconductor Corporation’s MoBL-USB FX2LP18 3.2 8051 Microprocessor (CY7C68053) is a low-voltage (1.8 volt) version of the EZ- The 8051 microprocessor embedded in the FX2LP18 family ® USB FX2LP (CY7C68013A), which is a highly integrated, has 256 bytes of register RAM, an expanded interrupt system, low-power USB 2.0 microcontroller. By integrating the USB 2.0 and three timer/counters. transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable
ページ3に含まれる内容の要旨
CY7C68053 Table 3-1. Special Function Registers x 8x 9x Ax Bx Cx Dx Ex Fx 0 IOA IOB IOC IOD SCON1 PSW ACC B 1SP EXIF INT2CLR IOE SBUF1 2DPL0 MPAGE OEA 3DPH0 OEB 4 DPL1 OEC 5 DPH1 OED 6 DPS OEE 7PCON 8 TCON SCON0 IE IP T2CON EICON EIE EIP 9TMOD SBUF0 ATL0 AUTOPTRH1 EP2468STAT EP01STAT RCAP2L BTL1 AUTOPTRL1 EP24FIFOFLGS GPIFTRIG RCAP2H CTH0 Reserved EP68FIFOFLGS TL2 DTH1 AUTOPTRH2 GPIFSGLDATH TH2 E CKCON AUTOPTRL2 GPIFSGLDATLX F Reserved AUTOPTRSET-UP GPIFSGLDATLNOX 2 3.3 I C™ Bus plugged in, wit
ページ4に含まれる内容の要旨
CY7C68053 pushes the program counter onto its stack then jumps to If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP address 0x0043, where it expects to find a ‘jump’ instruction to register), the FX2LP18 substitutes its INT2VEC byte. the USB interrupt service routine. Therefore, if the high byte (‘page’) of a jump-table address is preloaded at location 0x0044, the automatically-inserted The FX2LP18 jump instruction is encoded as shown in INT2VEC byte at 0x0045 directs the jump to the corre
ページ5に含まれる内容の要旨
CY7C68053 Figure 3-2. Reset Timing Plots RESET# RESET# V IL V IL 1.8V 1.8V 1.62V V V CC CC 0V 0V T T RESET RESET Power on Reset Powered Reset The FX2LP18 exits the power-down (USB suspend) state 3.9 Reset and Wakeup using one of the following methods: The reset and wakeup pins are described in detail in this • USB bus activity (if D+/D– lines are left floating, noise on section. these lines may indicate activity to the FX2LP18 and initiate 3.9.1 Reset Pin a wakeup) • External logic asserts the
ページ6に含まれる内容の要旨
CY7C68053 3.11 Register Addresses Figure 3-3. FX2LP18 Internal Code Memory Figure 3-4. Register Address Memory FFFF FFFF 7.5 kBytes 4 kBytes EP2-EP8 USB regs and buffers 4K FIFO buffers (8 x 512) E200 E1FF 0.5 kBytes RAM F000 Data E000 EFFF 2 kBytes RESERVED . E800 E7FF . 64 Bytes EP1IN E7C0 E7BF 64 Bytes EP1OUT . E780 E77F 64 Bytes EP0 IN/OUT E740 E73F 3FFF 64 Bytes RESERVED E700 E6FF 8051 Addressable Registers (512) 16 kBytes RAM E500 Code and Data E4FF Reserved (128) E480 E47F 128 Bytes GPIF
ページ7に含まれる内容の要旨
CY7C68053 vertical columns of Figure 3-5. When operating in full-speed 64 bytes are used. The unused endpoint buffer space is not BULK mode only the first 64 bytes of each buffer are used. For available for other operations. An example endpoint configu- example, in high-speed the maximum packet size is 512 bytes, ration is: but in full-speed it is 64 bytes. Even though a buffer is EP2–1024 double buffered; EP6–512 quad buffered configured to be a 512 byte buffer, in full-speed only the first (co
ページ8に含まれる内容の要旨
CY7C68053 3.12.6 Default High-Speed Alternate Settings [3, 4] Table 3-5. Default High-Speed Alternate Settings Alternate Setting 0 1 2 3 ep0 64 64 64 64 [5] ep1out 0 512 bulk 64 int 64 int [5] ep1in 0 512 bulk 64 int 64 int ep2 0 512 bulk out (2×) 512 int out (2×) 512 iso out (2×) ep4 0 512 bulk out (2×) 512 bulk out (2×) 512 bulk out (2×) ep6 0 512 bulk in (2×) 512 int in (2×) 512 iso in (2×) ep8 0 512 bulk in (2×) 512 bulk in (2×) 512 bulk in (2×) 3.13 External FIFO Interface In Slave (S) mod
ページ9に含まれる内容の要旨
CY7C68053 3.14.1 Three Control OUT Signals 3.16 USB Uploads and Downloads The 56-pin package brings out three of these signals, The core has the ability to directly edit the data contents of the CTL0–CTL2. The 8051 programs the GPIF unit to define the internal 16-kByte RAM and of the internal 512-byte scratch CTL waveforms. CTLx waveform edges can be programmed pad RAM via a vendor-specific command. This capability is to make transitions as fast as once per clock cycle (20.8 ns normally used whe
ページ10に含まれる内容の要旨
CY7C68053 0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The Table 3-6. Strap Boot EEPROM Address Lines to These 2 8051 is reset. I C interface boot loads only occur after power Values on reset. Bytes Example EEPROM A2 A1 A0 [8] 2 16 24AA00 N/A N/A N/A 3.18.3 I C Interface General Purpose Access 2 12824AA01 0 00 The 8051 can control peripherals connected to the I C bus 2 C using the I2CTL and I2DAT registers. FX2LP18 provides I 25624AA02 0 00 2 master control only, it is never an I C slave. 4
ページ11に含まれる内容の要旨
CY7C68053 Figure 4-2. CY7C68053 56-pin VFBGA Pin Assignment - Top view 12 34 5 678 1A 2A 3A 4A 5A 6A 7A 8A A 1B 2B 3B 4B 5B 6B 7B 8B B 1C 2C 3C 4C 5C 6C 7C 8C C D 1D 2D 7D 8D 1E 2E 7E 8E E 1F 2F 3F 4F 5F 6F 7F 8F F 1G 2G 3G 4G 5G 6G 7G 8G G H 1H 2H 3H 4H 5H 6H 7H 8H Document # 001-06120 Rev *F Page 11 of 39 [+] Feedback
ページ12に含まれる内容の要旨
CY7C68053 4.1 CY7C68053 Pin Descriptions [9] Table 4-1. FX2LP18 Pin Descriptions 56 VFBGA Name Type Default Description 2D AV Power N/A Analog VCC. Connect this pin to 3.3V power source. This signal provides CC power to the analog section of the chip. Appropriate bulk/bypass capacitance should be provided for this supply rail. 1D AV Power N/A Analog VCC. Connect this pin to 3.3V power source. This signal provides CC power to the analog section of the chip. 2F AGND Ground N/A Analog Ground.
ページ13に含まれる内容の要旨
CY7C68053 [9] Table 4-1. FX2LP18 Pin Descriptions (continued) 56 VFBGA Name Type Default Description 6F PA4 or I/O/Z I Multiplexed pin whose function is selected by: FIFOADR0 (PA4) IFCONFIG[1:0]. PA4 is a bidirectional IO port pin. FIFOADR0 is an input-only address select for the slave FIFO’s connected to FD[7:0] or FD[15:0]. 8C PA5 or I/O/Z I Multiplexed pin whose function is selected by: FIFOADR1 (PA5) IFCONFIG[1:0]. PA5 is a bidirectional IO port pin. FIFOADR1 is an input-only address sel
ページ14に含まれる内容の要旨
CY7C68053 [9] Table 4-1. FX2LP18 Pin Descriptions (continued) 56 VFBGA Name Type Default Description PORT D 8A PD0 or I/O/Z I Multiplexed pin whose function is selected by the IFCONFIG[1:0] and FD[8] (PD0) EPxFIFOCFG.0 (wordwide) bits. FD[8] is the bidirectional FIFO/GPIF data bus. 7A PD1 or I/O/Z I Multiplexed pin whose function is selected by the IFCONFIG[1:0] and FD[9] (PD1) EPxFIFOCFG.0 (wordwide) bits. FD[9] is the bidirectional FIFO/GPIF data bus. 6B PD2 or I/O/Z I Multiplexed pin whose
ページ15に含まれる内容の要旨
CY7C68053 [9] Table 4-1. FX2LP18 Pin Descriptions (continued) 56 VFBGA Name Type Default Description 2G IFCLK I/O/Z Z Interface Clock, used for synchronously clocking data into or out of the slave FIFO’s. IFCLK also serves as a timing reference for all slave FIFO control signals and GPIF. When internal clocking is used (IFCONFIG.7 = 1) the IFCLK pin can be configured to output 30/48 MHz by bits IFCONFIG.5 and IFCONFIG.6. IFCLK may be inverted, whether internally or externally sourced, by s
ページ16に含まれる内容の要旨
CY7C68053 5.0 Register Summary FX2LP18 register bit definitions are described in the MoBL-USB TRM in greater detail. Table 5-1. FX2LP18 Register Summary Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access GPIF Waveform Memories E400 128 WAVEDATA GPIF Waveform D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW Descriptor 0, 1, 2, 3 data E480 128 Reserved GENERAL CONFIGURATION E50D GPCR2 General Purpose Configu- Reserved Reserved Reserved FULL_SPEE Reserved Reserved Reserved Reserved 00000000 R
ページ17に含まれる内容の要旨
CY7C68053 Table 5-1. FX2LP18 Register Summary (continued) Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access E62C 1 ECC1B2 ECC1 Byte 2 Address COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16 00000000 R E62D 1 ECC2B0 ECC2 Byte 0 Address LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8 00000000 R E62E 1 ECC2B1 ECC2 Byte 1 Address LINE7 LINE6 LINE5 LINE4 LINE3 LINE2 LINE1 LINE0 00000000 R E62F 1 ECC2B2 ECC2 Byte 2 Address COL5 COL4 COL3 COL2 COL1 COL0 0 0 00000000 R [10] E630 1 EP2
ページ18に含まれる内容の要旨
CY7C68053 Table 5-1. FX2LP18 Register Summary (continued) Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access E65E 1 EPIE Endpoint Interrupt EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN 00000000 RW Enables [11] E65F 1 EPIRQ Endpoint Interrupt EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN 0 RW Requests [10] E660 1 GPIFIE GPIF Interrupt Enable 0 0 0 0 0 0 GPIFWF GPIFDONE 00000000 RW [10] E661 1 GPIFIRQ GPIF Interrupt Request 0 0 0 0 0 0 GPIFWF GPIFDONE 000000xx RW E662 1 USBERRIE USB Error
ページ19に含まれる内容の要旨
CY7C68053 Table 5-1. FX2LP18 Register Summary (continued) Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access E6A1 1 EP1OUTCS Endpoint 1 OUT Control 0 0 0 0 0 0 BUSY STALL 00000000 bbbbbbrb and Status E6A2 1 EP1INCS Endpoint 1 IN Control and 0 0 0 0 0 0 BUSY STALL 00000000 bbbbbbrb Status E6A3 1 EP2CS Endpoint 2 Control and 0 NPAK2 NPAK1 NPAK0 FULL EMPTY 0 STALL 00101000 rrrrrrrb Status E6A4 1 EP4CS Endpoint 4 Control and 0 0 NPAK1 NPAK0 FULL EMPTY 0 STALL 00101000 rrrrrrrb Status
ページ20に含まれる内容の要旨
CY7C68053 Table 5-1. FX2LP18 Register Summary (continued) Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access [10] E6CF 1 GPIFTCB2 GPIF Transaction Count TC23 TC22 TC21 TC20 TC19 TC18 TC17 TC16 00000000 RW Byte 2 [10] E6D0 1 GPIFTCB1 GPIF Transaction Count TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 00000000 RW Byte 1 [10] E6D1 1 GPIFTCB0 GPIF Transaction Count TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 00000001 RW Byte 0 2 Reserved 00000000 RW Reserved Reserved [10] E6D2 1 EP2GPIFFLGSEL Endpoint
