ページ1に含まれる内容の要旨
STK11C68
64 Kbit (8K x 8) SoftStore nvSRAM
Features Functional Description
■ 25 ns, 35 ns, and 45 ns access times The Cypress STK11C68 is a 64Kb fast static RAM with a nonvol-
atile element in each memory cell. The embedded nonvolatile
■ Pin compatible with industry standard SRAMs
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
■ Software initiated nonvolatile STORE
unlimited read and write cycles, while independent nonvolatil
ページ2に含まれる内容の要旨
STK11C68 Pin Configurations Figure 1. Pin Diagram - 28-Pin SOIC/DIP and 28-Pin LLC Pin Definitions Pin Name Alt IO Type Description A –A Input Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM. 0 12 DQ -DQ Input or Bidirectional Data IO Lines. Used as input or output lines depending on operation. 0 7 Output Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the W
ページ3に含まれる内容の要旨
STK11C68 not necessary that OE is LOW for a valid sequence. After the Device Operation t cycle time is fulfilled, the SRAM is again activated for STORE Read and Write operation. The STK11C68 is a versatile memory chip that provides several modes of operation. The STK16C88 can operate as a standard Software RECALL 8K x 8 SRAM. A 8K x 8 array of nonvolatile storage elements shadow the SRAM. SRAM data can be copied nonvolatile Data is transferred from the nonvolatile memory to the SRAM by memory or
ページ4に含まれる内容の要旨
STK11C68 average current drawn by the STK11C68 depends on the Best Practices following items: nvSRAM products have been used effectively for over 15 years. ■ The duty cycle of chip enable While ease of use is one of the product’s main system values, experience gained working with hundreds of applications has ■ The overall cycle rate for accesses resulted in the following suggestions as best practices: ■ The ratio of Reads to Writes ■ The nonvolatile cells in an nvSRAM are programmed on the ■ CM
ページ5に含まれる内容の要旨
STK11C68 Power Dissipation ......................................................... 1.0W Maximum Ratings DC Output Current (1 output at a time, 1s duration).... 15 mA Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Operating Range Storage Temperature ................................. –65 °C to +150 °C Ambient Range V CC Temperature under bias.............................. –55 °C to +125 °C Temperature Supply Voltage on V Relative to GN
ページ6に含まれる内容の要旨
STK11C68 Capacitance [3] In the following table, the capacitance parameters are listed. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25 °C, f = 1 MHz, 8pF IN A V = 0 to 3.0V CC C Output Capacitance 7pF OUT Thermal Resistance [3] In the following table, the thermal resistance parameters are listed. Parameter Description Test Conditions 28-SOIC 28-CDIP 28-LCC Unit Θ Thermal Resistance Test conditions follow standard test methods TBD TBD TBD °C/W JA (Junction to Ambient) a
ページ7に含まれる内容の要旨
STK11C68 AC Switching Characteristics SRAM Read Cycle Parameter 25 ns 35 ns 45 ns Description Unit Cypress Alt Min Max Min Max Min Max Parameter t t Chip Enable Access Time 25 35 45 ns ACE ELQV [4] t t t Read Cycle Time 25 35 45 ns RC AVAV, ELEH [5] t t Address Access Time 25 35 45 ns AA AVQV t t Output Enable to Data Valid 10 15 20 ns DOE GLQV [5] t t Output Hold After Address Change 5 5 5 ns OHA AXQX [6] t t Chip Enable to Output Active 5 5 5 ns LZCE ELQX [6] t t Chip Disable to Output Inact
ページ8に含まれる内容の要旨
STK11C68 SRAM Write Cycle Parameter 25 ns 35 ns 45 ns Description Unit Cypress Alt Min Max Min Max Min Max Parameter t t Write Cycle Time 25 35 45 ns WC AVAV t t t Write Pulse Width 20 25 30 ns PWE WLWH, WLEH t t t Chip Enable To End of Write 20 25 30 ns SCE ELWH, ELEH t t t Data Setup to End of Write 10 12 15 ns SD DVWH, DVEH t t t Data Hold After End of Write 0 0 0 ns HD WHDX, EHDX t t t Address Setup to End of Write 20 25 30 ns AW AVWH, AVEH t t t Address Setup to Start of Write 0 0 0 ns SA
ページ9に含まれる内容の要旨
STK11C68 AutoStore INHIBIT or Power Up RECALL STK11C68 Parameter Alt Description Unit Min Max [9] t t Power up RECALL Duration 550 μs HRECALL RESTORE t t STORE Cycle Duration 10 ms STORE HLHZ V Low Voltage Trigger Level 4.0 4.5 V SWITCH V Low Voltage Reset Level 3.6 V RESET Switching Waveform Figure 9. AutoStore INHIBIT/Power Up RECALL V CC 5V V SWITCH V RESET STORE INHIBIT POWER-UPRECALL t HRECALL DQ (DATA OUT) POWER-UP BROWN OUT BROWN OUT BROWN OUT RECALL STORE INHIBIT STORE INHIBIT STORE I
ページ10に含まれる内容の要旨
STK11C68 Software Controlled STORE/RECALL Cycle [10, 11] The software controlled STORE/RECALL cycle follows. 25 ns 35 ns 45 ns Parameter Alt Description Unit Min Max Min Max Min Max t t STORE/RECALL Initiation Cycle Time 25 35 45 ns RC AVAV [10] t t Address Setup Time 0 0 0 ns SA AVEL [10] t t Clock Pulse Width 20 25 30 ns CW ELEH [10] t t Address Hold Time 20 20 20 ns HACE ELAX [10] RECALL Duration 20 20 20 μs t RECALL Switching Waveform [11] Figure 10. CE Controlled Software STORE/RECALL Cy
ページ11に含まれる内容の要旨
STK11C68 Part Numbering Nomenclature STK11C68 - S F 45 I TR Packaging Option: TR = Tape and Reel Blank = Tube Temperature Range: Blank - Commercial (0 to 70°C) I - Industrial (-40 to 85°C) Speed: 25 - 25 ns 35 - 35 ns 45 - 45 ns Lead Finish F = 100% Sn (Matte Tin) Package: S = Plastic 28-pin 330 mil SOIC C = Ceramic 28-pin 300 mil DIP L = Ceramic 28-pin 350 mil LLC Ordering Information Speed (ns) Ordering Code Package Diagram Package Type Operating Range 25 STK11C68-SF25TR 001-85058 28-Pin SOI
ページ12に含まれる内容の要旨
STK11C68 Ordering Information (continued) Speed (ns) Ordering Code Package Diagram Package Type Operating Range 45 STK11C68-SF45TR 001-85058 28-Pin SOIC (330 mil) Commercial STK11C68-SF45 001-85058 28-Pin SOIC (330 mil) STK11C68-C45 001-51695 28-Pin CDIP (300 mil) STK11C68-L45 001-51696 28-Pin LCC (350 mil) STK11C68-SF45ITR 001-85058 28-Pin SOIC (330 mil) Industrial STK11C68-SF45I 001-85058 28-Pin SOIC (330 mil) STK11C68-C45I 001-51695 28-Pin CDIP (300 mil) STK11C68-L45I 001-51696 28-Pin LCC (35
ページ13に含まれる内容の要旨
STK11C68 Package Diagrams Figure 11. 28-Pin (330 Mil) SOIC (51-85058) 51-85058 *A Document Number: 001-50638 Rev. ** Page 13 of 16 [+] Feedback
ページ14に含まれる内容の要旨
STK11C68 Package Diagrams (continued) Figure 12. 28-Pin (300 Mil) Side Braze DIL (001-51695) 001-51695 ** Document Number: 001-50638 Rev. ** Page 14 of 16 [+] Feedback
ページ15に含まれる内容の要旨
STK11C68 Package Diagrams (continued) Figure 13. 28-Pad (350 Mil) LCC (001-51696) 1. ALL DIMENSION ARE IN INCHES AND MILLIMETERS [MIN/MAX] 2. JEDEC 95 OUTLINE# MO-041 001-51696 ** 3. PACKAGE WEIGHT : TBD Document Number: 001-50638 Rev. ** Page 15 of 16 [+] Feedback
ページ16に含まれる内容の要旨
STK11C68 Document History Page Document Title: STK11C68 64 Kbit (8K x 8) SoftStore nvSRAM Document Number: 001-50638 Orig. of Submission Rev. ECN No. Description of Change Change Date ** 2625084 GVCH/PYRS 01/30/09 New data sheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products P
