Freescale Semiconductor MPC5200Bの取扱説明書

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Table Of Contents Paragraph Page Number Number 20.8.8.1 Transmitting Or Receiving A Block Mode Message ...............................................................................20-45 20.8.8.2 Transmitting Or Receiving A Message In 4X Mode ................................................................................20-46 20.8.9 BDLC Module Initialization ..........................................................................................................................20-47 20.8.9.

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List of Figures Figure Page Number Number 1-1 Simplified Block Diagram—MPC5200 ....................................................................................................................1-4 1-2 MPC5200-Based System............................................................................................................................................1-6 2-1 272-Pin PBGA Pin Detail .........................................................................................................

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MPC5200B Users Guide
Document Number: MPC5200BUG
Rev. 1
05/2005

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Table of Contents Paragraph Page Number Number Chapter 1 Introduction 1.1 Overview ...................................................................................................................................................................1-1 1.1.1 Features ...............................................................................................................................................................1-1 1.2 Architecture .......................................................

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Table Of Contents Paragraph Page Number Number 4.2.2 Hard Reset—HRESET ........................................................................................................................................4-1 4.2.3 Soft Reset—SRESET ..........................................................................................................................................4-2 4.3 Reset Sequence ........................................................................................................

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Table of Contents Paragraph Page Number Number Chapter 7 System Integration Unit (SIU) 7.1 Overview ...................................................................................................................................................................7-1 7.2 Interrupt Controller ....................................................................................................................................................7-1 7.2.1 Block Description ................................

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Table Of Contents Paragraph Page Number Number 7.3.2.1.16 GPS GPIO Simple Interrupt Status Register—MBAR + 0x0B3C ......................................................7-44 7.3.2.2 WakeUp GPIO Registers—MBAR+0x0C00 ............................................................................................7-45 7.3.2.2.1 GPW WakeUp GPIO Enables Register—MBAR + 0x0C00 ...............................................................7-46 7.3.2.2.2 GPW WakeUp GPIO Open Drain Emulation Register —MBAR +

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Table of Contents Paragraph Page Number Number 8.4.4.3 Bank Active Command ..............................................................................................................................8-14 8.4.4.4 Read Command ..........................................................................................................................................8-14 8.4.4.5 Write Command ............................................................................................................

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Table Of Contents Paragraph Page Number Number 9.7.4.4 LPC Rx/Tx FIFO Alarm Register—MBAR + 0x3C4C ............................................................................9-30 9.7.4.5 LPC Rx/Tx FIFO Read Pointer Register—MBAR + 0x3C50 ..................................................................9-30 9.7.4.6 LPC Rx/Tx FIFO Write Pointer Register—MBAR + 0x3C54 ..................................................................9-31 Chapter 10 PCI Controller 10.1 Overview ...................

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Table of Contents Paragraph Page Number Number 10.3.3.1.4 Tx Enables PCITER(RW)—MBAR + 0x380C .................................................................................10-24 10.3.3.1.5 Tx Next Address PCITNAR(R) —MBAR + 0x3810 ........................................................................10-25 10.3.3.1.6 Tx Last Word PCITLWR(R) —MBAR + 0x3814 ............................................................................10-26 10.3.3.1.7 Tx Done Counts PCITDCR(R) —MBAR + 0x3818 ....

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Table Of Contents Paragraph Page Number Number 10.4.6.2 Addressing ................................................................................................................................................10-57 10.4.6.3 Data Translation .......................................................................................................................................10-57 10.4.6.4 Initialization ............................................................................................

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Table of Contents Paragraph Page Number Number 11.3.3.5 ATA Drive Error Register—MBAR + 0x3A64 .......................................................................................11-14 11.3.3.6 ATA Drive Sector Count Register—MBAR + 0x3A68 ...........................................................................11-15 11.3.3.7 ATA Drive Sector Number Register—MBAR + 0x3A6C .......................................................................11-15 11.3.3.8 ATA Drive Cylinder Low Register—MB

ページ11に含まれる内容の要旨

Table Of Contents Paragraph Page Number Number 12.4.3.2 USB HC Period Current Endpoint Descriptor Register —MBAR + 0x101C ..........................................12-13 12.4.3.3 USB HC Control Head Endpoint Descriptor Register —MBAR + 0x1020 ............................................12-14 12.4.3.4 USB HC Control Current Endpoint Descriptor Register —MBAR + 0x1024 ........................................12-14 12.4.3.5 USB HC Bulk Head Endpoint Descriptor Register—MBAR + 0x1028 ................

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Table of Contents Paragraph Page Number Number 13.12.22 SDMA Initiator Priority 24 Register—MBAR + 0x1254 ...............................................................................13-17 13.12.23 SDMA Initiator Priority 28 Register—MBAR + 0x1258 ...............................................................................13-18 13.12.24 SDMA Requestor MuxControl—MBAR + 0x125C ......................................................................................13-19 13.12.25 SDMA task Size0

ページ13に含まれる内容の要旨

Table Of Contents Paragraph Page Number Number 14.5.17 FEC Descriptor Individual Address 2 Register—MBAR + 0x311C ..............................................................14-24 14.5.18 FEC Descriptor Group Address 1 Register—MBAR + 0x3120 .....................................................................14-25 14.5.19 FEC Descriptor Group Address 2 Register—MBAR + 0x3124 .....................................................................14-25 14.5.20 FEC Tx FIFO Watermark Register—MBAR

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Table of Contents Paragraph Page Number Number 15.2.14 Codec Clock Register (0x20)—CCR ..............................................................................................................15-21 15.2.15 Interrupt Vector Register (0x30)—IVR ..........................................................................................................15-23 15.2.16 Input Port Register (0x34)—IP ......................................................................................................

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Table Of Contents Paragraph Page Number Number 15.3.3.4 Configuration Sequence for AC97 Mode .................................................................................................15-58 15.3.4 PSC in SIR Mode ............................................................................................................................................15-58 15.3.4.1 Block Diagram and Signal Definition for SIR Mode .............................................................................

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Table of Contents Paragraph Page Number Number Chapter 17 Serial Peripheral Interface (SPI) 17.1 Overview .................................................................................................................................................................17-1 17.1.1 Features .............................................................................................................................................................17-1 17.1.2 Modes of Operation ........................

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Table Of Contents Paragraph Page Number Number 19.5.4 MSCAN Control Register 1 (CANCTL1)—MBAR + 0x0901 ........................................................................19-6 19.5.5 MSCAN Bus Timing Register 0 (CANBTR0)—MBAR + 0x0904 .................................................................19-8 19.5.6 MSCAN Bus Timing Register 1 (CANBTR1)—MBAR + 0x0905 .................................................................19-8 19.5.7 MSCAN Receiver Flag Register (CANRFLG)—MBAR+0x0908 ....

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Table of Contents Paragraph Page Number Number Chapter 20 Byte Data Link Controller (BDLC) 20.1 Overview .................................................................................................................................................................20-1 20.2 Features ...................................................................................................................................................................20-1 20.3 Modes of Operation .......................