ページ1に含まれる内容の要旨
80C186EA/80C188EA AND 80L186EA/80L188EA
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS
Y
80C186 Upgrade for Power Critical Applications
Y
Fully Static Operation
Y
True CMOS Inputs and Outputs
Y Y
Integrated Feature Set Speed Versions Available (3V):
Ð Static 186 CPU Core Ð 13 MHz (80L186EA13/80L188EA13)
Ð Power Save, Idle and Powerdown Ð 8 MHz (80L186EA8/80L188EA8)
Modes
Y
Direct Addressing Capability to
Ð Clock Generator
1 Mbyte Memory and 64 Kbyte I/O
Ð 2 Independent DMA Channels
Y
Supports 80C18
ページ2に含まれる内容の要旨
80C186EA/80C188EA, 80L186EA/80L188EA 80C186EA/80C188EA AND 80L186EA/80L188EA 16-Bit High Integration Embedded Processor CONTENTS PAGE CONTENTS PAGE INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 PACKAGE THERMAL SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20 80C186EA CORE ARCHITECTURE ÀÀÀÀÀÀÀ 4 ELECTRICAL SPECIFICATIONS ÀÀÀÀÀÀÀÀÀ 21 Bus Interface Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21 Clock Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 Recommended Connections ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ
ページ3に含まれる内容の要旨
80C186EA/80C188EA, 80L186EA/80L188EA NOTE: Pin names in parentheses apply to the 80C186EA/80L188EA Figure 1. 80C186EA/80C188EA Block Diagram 3 3 272432±2
ページ4に含まれる内容の要旨
80C186EA/80C188EA, 80L186EA/80L188EA INTRODUCTION 80C186EA CORE ARCHITECTURE Unless specifically noted, all references to the 80C186EA apply to the 80C188EA, 80L186EA, and Bus Interface Unit 80L188EA. References to pins that differ between The 80C186EA core incorporates a bus controller the 80C186EA/80L186EA and the 80C188EA/ that generates local bus control signals. In addition, 80L188EA are given in parentheses. The ``L'' in the it employs a HOLD/HLDA protocol to share the local part number de
ページ5に含まれる内容の要旨
80C186EA/80C188EA, 80L186EA/80L188EA 272432±4 272432±3 (A) Crystal Connection (B) Clock Connection NOTE: The L C network is only required when using a third-overtone crystal. 1 1 Figure 2. Clock Configurations 80C186EA PERIPHERAL Interrupt Control Unit ARCHITECTURE The 80C186EA can receive interrupts from a num- ber of sources, both internal and external. The Inter- The 80C186EA has integrated several common sys- rupt Control Unit (ICU) serves to merge these re- tem peripherals with a CPU core t
ページ6に含まれる内容の要旨
80C186EA/80C188EA, 80L186EA/80L188EA PCB PCB PCB PCB Function Function Function Function Offset Offset Offset Offset 00H Reserved 40H Reserved 80H Reserved C0H DMA0 Src. Lo 02H Reserved 42H Reserved 82H Reserved C2H DMA0 Src. Hi 04H Reserved 44H Reserved 84H Reserved C4H DMA0 Dest. Lo 06H Reserved 46H Reserved 86H Reserved C6H DMA0 Dest. Hi 08H Reserved 48H Reserved 88H Reserved C8H DMA0 Count 0AH Reserved 4AH Reserved 8AH Reserved CAH DMA0 Control 0CH Reserved 4CH Reserved 8CH Reserved CCH Rese
ページ7に含まれる内容の要旨
80C186EA/80C188EA, 80L186EA/80L188EA Chip-Select Unit PCB Function Offset The 80C186EA Chip-Select Unit integrates logic which provides up to 13 programmable chip-selects 20H Interrupt Vector to access both memories and peripherals. In addi- 22H Specific EOI tion, each chip-select can be programmed to auto- matically terminate a bus cycle independent of the 24H Reserved condition of the SRDY and ARDY input pins. The 26H Reserved chip-select lines are available for all memory and I/O bus cycles,
ページ8に含まれる内容の要旨
80C186EA/80C188EA, 80L186EA/80L188EA The 80-lead QFP (EIAJ) pinouts are different be- 80C187 Interface (80C186EA Only) tween the 80C186XL and the 80C186EA. In addition to the PDTMR pin, the 80C186EA has more power The 80C187 Numerics Coprocessor may be used to and ground pins and the overall arrangement of pins extend the 80C186EA instruction set to include was shifted. A new circuit board layout for the floating point and advanced integer instructions. 80C186EA is required. Connecting the 80C18
ページ9に含まれる内容の要旨
80C186EA/80C188EA, 80L186EA/80L188EA input/output (I/O). Some pins have multiplexed PACKAGE INFORMATION functions (for example, A19/S6). Additional symbols indicate additional characteristics for each pin. Table This section describes the pins, pinouts, and thermal 3 lists all the possible symbols for this column. characteristics for the 80C186EA in the Plastic Leaded Chip Carrier (PLCC) package, Shrink Quad The Input Type column indicates the type of input Flat Pack (SQFP), and Quad Flat Pack (
ページ10に含まれる内容の要旨
80C186EA/80C188EA, 80L186EA/80L188EA Table 2. Pin Description Nomenclature Symbol Description a P Power Pin (Apply V Voltage) CC G Ground (Connect to V ) SS I Input Only Pin O Output Only Pin I/O Input/Output Pin S(E) Synchronous, Edge Sensitive S(L) Synchronous, Level Sensitive A(E) Asynchronous, Edge Sensitive A(L) Asynchronous, Level Sensitive H(1) Output Driven to V during Bus Hold CC H(0) Output Driven to V during Bus Hold SS H(Z) Output Floats during Bus Hold H(Q) Output Remains Active dur
ページ11に含まれる内容の要旨
80C186EA/80C188EA, 80L186EA/80L188EA Table 3. Pin Descriptions Pin Pin Input Output Description Name Type Type States V P POWER connections consist of six pins which must be shorted CC externally to a V board plane. CC V G GROUND connections consist of five pins which must be shorted SS externally to a V board plane. SS CLKIN I A(E) CLocK INput is an input for an external clock. An external oscillator operating at two times the required processor operating frequency can be connected to CLKIN. Fo
ページ12に含まれる内容の要旨
80C186EA/80C188EA, 80L186EA/80L188EA Table 3. Pin Descriptions (Continued) Pin Pin Input Output Description Name Type Type States A18:16 O H(Z) These pins provide multiplexed Address during the address phase of the bus cycle. Address bits 16 through 19 are A19/S6±A16 R(Z) presented on these pins and can be latched using ALE. (A19±A8) P(X) A18:16 are driven to a logic 0 during the data phase of the bus cycle. On the 8-bit bus versions, A15±A8 provide valid address information for the entire bus c
ページ13に含まれる内容の要旨
80C186EA/80C188EA, 80L186EA/80L188EA Table 3. Pin Descriptions (Continued) Pin Pin Input Output Description Name Type Type States WR/QS1 O H(Z) WRite output signals that data available on the data bus are to be written into the accessed memory or I/O device. In Queue Status R(Z) Mode, QS1 provides queue status information along with QS0. P(1) ARDY I A(L) Asychronous ReaDY is an input to signal for the end of a bus cycle. S(L) ARDY is asynchronous on rising CLKOUT and synchronous on falling CLKOU
ページ14に含まれる内容の要旨
80C186EA/80C188EA, 80L186EA/80L188EA Table 3. Pin Descriptions (Continued) Pin Pin Input Output Description Name Type Type States MCS0/PEREQ I/O A(L) H(1) These pins provide a multiplexed function. If enabled, these pins normally comprise a block of Mid-Range Chip MCS1/ERROR R(1) Select outputs which will go active whenever the address MCS2 P(1) of a memory bus cycle is within the address limitations MCS3/NCS programmed by the user. In Numerics Mode (80C186EA only), three of the pins become hand
ページ15に含まれる内容の要旨
80C186EA/80C188EA, 80L186EA/80L188EA 80C186EA/80C188EA (EIAJ QFP package) as 80C186EA PINOUT viewed from the top side of the component (i.e., con- tacts facing down). Tables 4 and 5 list the 80C186EA pin names with package location for the 68-pin Plastic Leaded Chip Tables 8 and 9 list the 80C186EA/80C188EA pin Carrier (PLCC) component. Figure 9 depicts the names with package location for the 80-pin Shrink complete 80C186EA/80L186EA pinout (PLCC pack- Quad Flat Pack (SQFP) component. Figure 7 de
ページ16に含まれる内容の要旨
80C186EA/80C188EA, 80L186EA/80L188EA Table 5. PLCC Package Location with Pin Names Location Name Location Name Location Name Location Name 1 AD15 (A15) 18 DRQ0 35 MCS3/NCS 52 S0 2 AD7 19 DRQ1 36 MCS2 53 S1 3 AD14 (A14) 20 T0IN 37 MCS1/ERROR 54 S2 4 AD6 21 T1IN 38 MCS0/PEREQ 55 ARDY 5 AD13 (A13) 22 T0OUT 39 DEN 56 CLKOUT 6 AD5 23 T1OUT 40 PDTMR 57 RESOUT 7 AD12 (A12) 24 RESIN 41 INT3/INTA1/ 58 OSCOUT 8 AD4 25 PCS0 IRQ 59 CLKIN 9V 26 V 42 INT2/INTA0 60 V CC SS SS 10 AD11 (A11) 27 PCS1 43 V 61 ALE/
ページ17に含まれる内容の要旨
80C186EA/80C188EA, 80L186EA/80L188EA Table 6. QFP (EIAJ) Pin Names with Package Location Address/Data Bus Bus Control Processor Control I/O Name Location Name Location Name Location Name Location AD0 64 ALE/QS0 10 RESIN 55 UCS 45 AD1 66 BHE (RFSH) 7 RESOUT 18 LCS 46 AD2 68 S0 23 CLKIN 16 MCS0/PEREQ 40 AD3 70 S1 22 OSCOUT 17 MCS1/ERROR 41 AD4 74 S2 21 CLKOUT 19 MCS2 42 AD5 76 RD/QSMD 9 TEST/BUSY 29 MCS3/NCS 43 AD6 78 WR/QS1 8 PDTMR 38 PCS0 54 AD7 80 ARDY 20 NMI 30 PCS1 52 AD8 (A8) 65 SRDY 27 INT0
ページ18に含まれる内容の要旨
80C186EA/80C188EA, 80L186EA/80L188EA Table 7. QFP (EIAJ) Package Location with Pin Names Location Name Location Name Location Name Location Name 1 AD15 (A15) 21 S2 41 MCS1/ERROR 61 DRQ0 2V 22 S1 42 MCS2 62 V CC SS 3 A16 23 S0 43 MCS3/NCS 63 N.C. 4 A17 24 V 44 V 64 AD0 SS CC 5 A18 25 HLDA 45 UCS 65 AD8 (A8) 6 A19/S6 26 HOLD 46 LCS 66 AD1 7 BHE (RFSH) 27 SRDY 47 PCS6/A2 67 AD9 (A9) 8WR/QS1 28 LOCK 48 PCS5/A1 68 AD2 9RD/QSMD 29 TEST/BUSY 49 PCS4 69 AD10 (A10) 10 ALE/QS0 30 NMI 50 PCS3 70 AD3 11 N.C
ページ19に含まれる内容の要旨
80C186EA/80C188EA, 80L186EA/80L188EA Table 8. SQFP Pin Functions with Package Location AD Bus Bus Control Processor Control I/O AD0 1 ALE/QS0 29 RESIN 73 UCS 62 AD1 3 BHE/(RFSH)26 RESOUT 34 LCS 63 AD2 6 S0 40 CLKIN 32 AD3 8 S1 39 OSCOUT 33 MCS0/PEREQ 57 AD4 12 S2 38 CLKOUT 36 MCS1/ERROR 58 AD5 14 RD/QSMD 28 TEST/BUSY 46 MCS2 59 AD6 16 WR/QS1 27 NMI 47 MCS3/NPS 60 AD7 18 ARDY 37 INT0 48 AD8 (A8) 2 SRDY 44 INT1/SELECT 49 PCS0 71 AD9 (A9) 5 DEN 56 INT2/INTA0 52 PCS1 69 AD10 (A10) 7 DT/R 54 INT3/INT
ページ20に含まれる内容の要旨
80C186EA/80C188EA, 80L186EA/80L188EA 272432±7 Figure 7. Shrink Quad Flat Pack (SQFP) Pinout Diagram NOTES: 1. XXXXXXXXD indicates the Intel FPO number. 2. Pin names in parentheses apply to the 80C188EA. T (the ambient temperature) can be calculated A PACKAGE THERMAL from i (thermal resistance from the case to ambi- CA SPECIFICATIONS ent) with the following equation: The 80C186EA/80L186EA is specified for operation e c T T -P i A C CA when T (the case temperature) is within the range C of 0§Cto85
