ページ1に含まれる内容の要旨
Date : 28 November 2005
HARDWARE REFERENCE GUIDE Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
Page : 1
Hardware Reference Guide
®
micro-line C6713CPU
High performance DSP / FPGA board
Orsys Orth System GmbH, Am Stadtgraben 25, 88677 Markdorf, Germany http://www.orsys.de
ページ2に含まれる内容の要旨
Date : 28 November 2005 HARDWARE REFERENCE GUIDE Doc. no. : C6713CPU_HRG ® Iss./Rev : 1.1 MICRO-LINE C6713CPU Page : 2 Contents 1 PREFACE......................................................................................................................6 1.1 Document Organization.........................................................................................................6 1.2 Documentation Overview ...........................................................
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Date : 28 November 2005 HARDWARE REFERENCE GUIDE Doc. no. : C6713CPU_HRG ® Iss./Rev : 1.1 MICRO-LINE C6713CPU Page : 3 3.3 Internal fast SRAM ...............................................................................................................21 3.4 DSP Peripherals ...................................................................................................................21 3.5 External SDRAM ...............................................................
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Date : 28 November 2005 HARDWARE REFERENCE GUIDE Doc. no. : C6713CPU_HRG ® Iss./Rev : 1.1 MICRO-LINE C6713CPU Page : 4 7.2.3 Configuring for HPI or McASP1 Usage ...............................................................................47 ® 7.2.4 Configuring micro-line Pin D30 Termination ......................................................................47 2 7.2.5 Configuring for I C interface #0 Operation ..........................................................
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Date : 28 November 2005 HARDWARE REFERENCE GUIDE Doc. no. : C6713CPU_HRG ® Iss./Rev : 1.1 MICRO-LINE C6713CPU Page : 5 List of Tables Table 1: Memory map of the processor...........................................................................................20 Table 2: Memory map of the C6713CPU ........................................................................................21 Table 3: default initialization values for the FPGA related CE space registers .....
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Date : 28 November 2005 HARDWARE REFERENCE GUIDE Doc. no. : C6713CPU_HRG ® Iss./Rev : 1.1 MICRO-LINE C6713CPU Page : 6 1 Preface This document describes the hardware of the C6713CPU board. It is intended to get an overview of the board and its features. Detailed information about programming, usage of the FPGA and the DSP is described in other documents that will be referenced throughout this document. 1.1 Document Organization This document is organized as follows: •
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Date : 28 November 2005 HARDWARE REFERENCE GUIDE Doc. no. : C6713CPU_HRG ® Iss./Rev : 1.1 MICRO-LINE C6713CPU Page : 7 Configuration parameters, function names, path names and file names are written in italic typeface. Example: dev_id Source code examples are given in a small, fixed-width typeface. Example: int a = 10; Menus and commands from menus and submenus are enclosed in double-quotes. Example: Create a new project using the "Create Project..." command from th
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Date : 28 November 2005 HARDWARE REFERENCE GUIDE Doc. no. : C6713CPU_HRG ® Iss./Rev : 1.1 MICRO-LINE C6713CPU Page : 8 1.5 Revision History Revision Changes 0.1 ORSYS internal preliminary version / April 2005 0.5 First public preliminary version / May 2005 0.9 Completely revised. Block diagram completed. 1.0 Flash File System: short description only, reference to separate user's guide. Mentioned that HPI usage requires FPGA. Minor corrections to signal descriptions:
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Date : 28 November 2005 HARDWARE REFERENCE GUIDE Doc. no. : C6713CPU_HRG ® Iss./Rev : 1.1 MICRO-LINE C6713CPU Page : 9 2 Hardware Overview ® The micro-line C6713CPU is a high performance DSP board that combines several key technologies for high speed data processing: • a TMS320C6713 DSP with 256 KB internal fast SRAM and 225MHz or 300MHz CPU clock (1800 MIPS / 1350 MFLOPS or 2400 MIPS / 1800 MFLOPS) • a Xilinx Spartan 3 FPGA with up to 1M gates • 32 / 64 MB SDRAM in s
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Date : 28 November 2005 HARDWARE REFERENCE GUIDE Doc. no. : C6713CPU_HRG ® Iss./Rev : 1.1 MICRO-LINE C6713CPU Page : 10 2.1 Block Diagram of the C6713CPU Figure 1: Block diagram of the C6713CPU
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Date : 28 November 2005 HARDWARE REFERENCE GUIDE Doc. no. : C6713CPU_HRG ® Iss./Rev : 1.1 MICRO-LINE C6713CPU Page : 11 flash memory FPGA green LED (PLD) red LED (PLD) yellow LED (FPGA) JTAG connector PLD micro-line connectors temperature DSP SDRAM sensor Figure 2: Top side of the C6713CPU 16 bit HPI data bus transceiver micro-line connectors SDRAM Figure 3: Bottom side of the C6713CPU R1 C9
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Date : 28 November 2005 HARDWARE REFERENCE GUIDE Doc. no. : C6713CPU_HRG ® Iss./Rev : 1.1 MICRO-LINE C6713CPU Page : 12 2.2 Connectors ® 2.2.1 micro-line Connectors ® The micro-line connectors are the main I/O connectors of the C6713CPU. They provide access to ® all signals that are needed for a wide range of I/O connectivity. The signals on the micro-line connectors can be grouped into the following categories: • power supply • DSP- and board specific interfaces, suc
ページ13に含まれる内容の要旨
Date : 28 November 2005 HARDWARE REFERENCE GUIDE Doc. no. : C6713CPU_HRG ® Iss./Rev : 1.1 MICRO-LINE C6713CPU Page : 13 ® interfacing over for the majority of the micro-line connector pins. The user is no longer restricted to a fixed I/O logic. The FPGA has access to the following signal groups: • DSP EMIF (data bus, address bus, control signals) ® • micro-line connectors • JTAG interface • DSP interrupts • RS232 line driver The figure below gives an overview, h
ページ14に含まれる内容の要旨
Date : 28 November 2005 HARDWARE REFERENCE GUIDE Doc. no. : C6713CPU_HRG ® Iss./Rev : 1.1 MICRO-LINE C6713CPU Page : 14 can be software reconfigured by PLL settings. It can also be generated by the FPGA, allowing any clock frequency up to 100 MHz. Compared to the internal fast SRAM of the DSP chip, the on-board SDRAM is significantly slower. Therefore it is strongly recommended to use the internal memory of the DSP whenever it is possible. The internal memory can be use
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Date : 28 November 2005 HARDWARE REFERENCE GUIDE Doc. no. : C6713CPU_HRG ® Iss./Rev : 1.1 MICRO-LINE C6713CPU Page : 15 DSP-internal temperature is roughly 15 degrees Celsius above the temperature measured by the sensor. Software drivers for the temperature sensor are included in the development kits, see [20] for details. Further information can be found in [18]. 2 The temperature sensor is connected to the PLD by a separate I C interface. It does not use the 2 2 I C i
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Date : 28 November 2005 HARDWARE REFERENCE GUIDE Doc. no. : C6713CPU_HRG ® Iss./Rev : 1.1 MICRO-LINE C6713CPU Page : 16 2.4.1 User Programmable LED's (PLD) These LED's are controlled by PLD registers (see chapter 3.10). They can be switched on and off by application software to display certain events or states. Examples for software controlled usage of the LED's are: • displaying an error condition by the red LED • checking software activity by toggling one of the L
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Date : 28 November 2005 HARDWARE REFERENCE GUIDE Doc. no. : C6713CPU_HRG ® Iss./Rev : 1.1 MICRO-LINE C6713CPU Page : 17 • CE0 is used for on-board SDRAM • CE1 is used for on-board flash memory , PLD and FPGA registers. • CE2 and CE3 are used for the FPGA Please refer to chapter 3 for further descriptions of the CE spaces and their address ranges. 2 2.5.3 Inter Integrated Circuit (I C) Interfaces 2 The TMS320C6713 DSP provides two I C interfaces. These 2-wire interfac
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Date : 28 November 2005 HARDWARE REFERENCE GUIDE Doc. no. : C6713CPU_HRG ® Iss./Rev : 1.1 MICRO-LINE C6713CPU Page : 18 2.5.6 Timers The TMS320C6713 DSP provides two independent 32-bit general purpose timers. The timers support two signaling modes and can be clocked by an internal or an external source. Each timer has a separate input pin and an output pin. Using an internal clock, for example, the timer can trigger an external A/D converter to start a conversion, or it
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Date : 28 November 2005 HARDWARE REFERENCE GUIDE Doc. no. : C6713CPU_HRG ® Iss./Rev : 1.1 MICRO-LINE C6713CPU Page : 19 2.5.9 DMA The TMS320C6713 DSP provides an enhanced DMA (EDMA) controller with 16 channels and 16 possible synchronization events. It can be used to transfer data between two locations anywhere in the address range of the C6713CPU. EDMA transfers can be triggered by software, internal events, such as timers or serial ports, or by hardware interrupt line
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Date : 28 November 2005 HARDWARE REFERENCE GUIDE Doc. no. : C6713CPU_HRG ® Iss./Rev : 1.1 MICRO-LINE C6713CPU Page : 20 3 Memory Maps and Description of the PLD Registers 3.1 TMS320C6713 Memory Map The memory map of the TMS320C6713 is divided into several sections: • internal memory • DSP peripherals • EMIF CE spaces CE0 .. CE3 The external devices are located at different CE (Chip Enable) spaces. The EMIF bus timing of each CE space can be individually set up. T
