ページ1に含まれる内容の要旨
DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD75P3116
4-BIT SINGLE-CHIP MICROCONTROLLER
The µ PD75P3116 replaces the µ PD753108’s internal mask ROM with a one-time PROM, and features expanded
ROM capacity.
Because the µ PD75P3116 supports programming by users, it is suitable for use in evaluation of systems in the
development stage using the µ PD753104, 753106, or 753108, and for use in small-scale production.
Detailed information about functions is provided in the following User’s Manual. Be sure to
ページ2に含まれる内容の要旨
µ PD75P3116 FUNCTION OUTLINE Item Function Instruction execution time • 0.95, 1.91, 3.81, or 15.3 µ s (main system clock: @ 4.19 MHz) • 0.67, 1.33, 2.67, or 10.7 µ s (main system clock: @ 6.0 MHz) • 122 µ s (subsystem clock: @ 32.768 kHz) Internal memory PROM 16384 × 8 bits RAM 512 × 4 bits General-purpose registers • 4-bit manipulation: 8 × 4 banks • 8-bit manipulation: 4 × 4 banks I/O ports CMOS input 8 Internal pull-up resistor connection can be specified by software setting: 7 CMOS I/O 20
ページ3に含まれる内容の要旨
µ PD75P3116 CONTENTS 1. PIN CONFIGURATION (TOP VIEW)................................................................................................. 4 2. BLOCK DIAGRAM ............................................................................................................................ 6 3. PIN FUNCTIONS ............................................................................................................................... 7 3.1 Port Pins ...........................................
ページ4に含まれる内容の要旨
µ PD75P3116 1. PIN CONFIGURATION (TOP VIEW) • 64-pin plastic QFP (14 × 14): µ PD75P3116GC-AB8 • 64-pin plastic LQFP (12 × 12): µ PD75P3116GK-8A8 • 64-pin plastic LQFP (14 × 14): µ PD75P3116GC-8BS 64636261605958575655545352515049 BIAS 1 48 S12 VLC0 2 47 S13 VLC1 3 46 S14 VLC2 4 45 S15 P30/LCDCL/MD0 5 44 P93/S16 P31/SYNC/MD1 6 43 P92/S17 P32/MD2 7 42 P91/S18 P33/MD3 8 41 P90/S19 Vss 9 40 P83/S20 P50/D4 10 39 P82/S21 P51/D5 11 38 P81/S22 P52/D6 12 37 P80/S23 P53/D7 13 36 P23/BUZ P60/KR0/D0 14 35 P2
ページ5に含まれる内容の要旨
µ PD75P3116 PIN IDENTIFICATIONS P00 to P03: Port 0 COM0 to COM3: Common output 0 to 3 P10 to P13: Port 1 VLC0 to VLC2: LCD power supply 0 to 2 P20 to P23: Port 2 BIAS: LCD power supply bias control P30 to P33: Port 3 LCDCL: LCD clock P50 to P53: Port 5 SYNC: LCD synchronization P60 to P63: Port 6 TI0 to TI2: Timer input 0 to 2 P80 to P83: Port 8 PTO0 to PTO2: Programmable timer output 0 to 2 P90 to P93: Port 9 BUZ: Buzzer clock KR0 to KR3: Key return 0 to 3 PCL: Programmable clock SCK: Serial cl
ページ6に含まれる内容の要旨
µ PD75P3116 2. BLOCK DIAGRAM Port 0 4 P00 to P03 Watch BUZ/P23 timer INTW fLCD Port 1 4 P10 to P13 SP (8) Program Basic counter (14) CY interval SBS timer/ ALU Port 2 4 P20 to P23 watchdog timer Bank P30/MD0 to INTBT Port 3 4 P33/MD3 TI0/P13 8-bit timer/event P50/D4 to PTO0/P20 Port 5 4 counter #0 P53/D7 General- INTT0 TOUT0 purpose INTT1 P60/D0 to Port 6 4 TI1/TI2/ register P63/D3 8-bit P12/INT2 Cascaded timer/event Program 16-bit PTO1/P21 counter #1 memory Port 8 4 P80 to P83 timer/ Decode (PR
ページ7に含まれる内容の要旨
µ PD75P3116 3. PIN FUNCTIONS 3.1 Port Pins (1/2) Pin Name I/O Alternate Function 8-Bit Status I/O Circuit Note 1 Function I/O After Reset Type P00 Input INT4 4-bit input port (Port 0) — Input Connection of an internal pull-up resistor can be P01 SCK specified by a software setting in 3-bit units. -A P02 SO/SB0 -B P03 SI/SB1 -C P10 Input INT0 4-bit input port (Port 1) — Input -C Connection of an internal pull-up resistor can be P11 INT1 specified by a software setting in 4-bit uni
ページ8に含まれる内容の要旨
µ PD75P3116 3.1 Port Pins (2/2) Pin Name I/O Alternate Function 8-Bit Status I/O Circuit Note 1 Function I/O After Reset Type P60 I/O KR0/D0 Programmable 4-bit I/O port (Port 6) — Input -A Input and output can be specified in 1-bit units. P61 KR1/D1 Connection of an internal pull-up resistor can be specified by a software setting in 4-bit units. P62 KR2/D2 P63 KR3/D3 P80 I/O S23 4-bit I/O port (Port 8) √ Input H Connection of an internal pull-up resistor can be Note 2 P81 S22 specified by a s
ページ9に含まれる内容の要旨
µ PD75P3116 3.2 Non-Port Pins (1/2) Pin Name I/O Alternate Function Status I/O Circuit Note 1 Function After Reset Type TI0 Input P13 External event pulse input to timer/event counter Input -C TI1 P12/INT2/TI2 TI2 P12/INT2/TI1 PTO0 Output P20 Timer/event counter output Input E-B PTO1 P21 PTO2 P22/PCL PCL P22/PTO2 Clock output BUZ P23 Frequency output (for buzzer or system clock trimming) SCK I/O P01 Serial clock I/O Input -A SO/SB0 P02 Serial data output -B Serial data bus I/O SI/SB1 P0
ページ10に含まれる内容の要旨
µ PD75P3116 3.2 Non-Port Pins (2/2) Pin Name I/O Alternate Function Status I/O Circuit Function After Reset Type S0 to S15 Output — Segment signal output Note 1 G-A S16 to S19 Output P93 to P90 Segment signal output Input H S20 to S23 Output P83 to P80 Segment signal output Input H COM0 to COM3 Output — Common signal output Note 1 G-B VLC0 to VLC2 — — Power supply for driving LCD — — BIAS Output — Output for external split resistor cut Note 2 — Note 3 LCDCL Output P30/MD0 Clock output for drivin
ページ11に含まれる内容の要旨
µ PD75P3116 3.3 Pin I/O Circuits The I/O circuits for the µ PD75P3116’s pins are shown in abbreviated form below. Type A Type D VDD VDD Data P-ch OUT P-ch IN Output N-ch N-ch disable Push-pull output that can be set to high impedance output CMOS standard input buffer (with both P-ch and N-ch OFF). Type B Type E-B VDD P.U.R. P.U.R. P-ch enable IN Data IN/OUT Type D Output disable Type A Schmitt-triggered input with hysteresis characteristics. P.U.R. : Pull-Up Resistor Type B-C Type F-A VDD VDD P.
ページ12に含まれる内容の要旨
µ PD75P3116 (Continued) Type F-B Type H VDD P.U.R. P.U.R. P-ch enable Output VDD P-ch IN/OUT SEG disable Type G-A data N-ch (P) P-ch IN/OUT Data Output N-ch disable Data Output Type E-B Output disable disable (N) P.U.R. : Pull-Up Resistor Type G-A Type M-C VDD P-ch VLC0 N-ch P.U.R. P-ch VLC1 P.U.R. P-ch N-ch enable P-ch N-ch IN/OUT Data OUT N-ch Output SEG N-ch data disable P-ch VLC2 N-ch N-ch P.U.R. : Pull-Up Resistor Type G-B Type M-E IN/OUT Data P-ch N-ch VLC0 N-ch (+13 V Output withstand-
ページ13に含まれる内容の要旨
µ PD75P3116 3.4 Recommended Connection of Unused Pins Table 3-1. List of Unused Pin Connections Pin Recommended Connection P00/INT4 Connect to Vss or VDD. P01/SCK Input: Independently connect to Vss or VDD via a resistor. P02/SO/SB0 Output: Leave open. P03/SI/SB1 Connect to Vss. P10/INT0 and P11/INT1 Connect to Vss or VDD. P12/TI1/TI2/INT2 P13/TI0 P20/PTO0 Input: Independently connect to Vss or VDD via a resistor. P21/PTO1 Output: Leave open. P22/PTO2/PCL P23/BUZ P30/LCDCL/MD0 P31/SYNC/MD1 P32/
ページ14に含まれる内容の要旨
µ PD75P3116 4. Mk I AND Mk II MODE SELECTION FUNCTION Setting the stack bank selection (SBS) register for the µ PD75P3116 enables the program memory to be switched between the Mk I mode and Mk II mode. This function is applicable when using the µ PD75P3116 to evaluate the µ PD753104, 753106, or 753108. When bit 3 of SBS is set to 1: Sets the Mk I mode (supports the Mk I mode for the µ PD753104, 753106, and 753108) When bit 3 of SBS is set to 0: Sets the Mk II mode (supports the Mk II mode for t
ページ15に含まれる内容の要旨
µ PD75P3116 4.2 Setting of Stack Bank Selection (SBS) Register Use the stack bank selection register to switch between the Mk I mode and Mk II mode. Figure 4-1 shows the format of the stack bank selection register. The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be Note sure to initialize the stack bank selection register to 100×B at the beginning of the program. When using the Mk II mode, Note be sure to initialize it to 000×B
ページ16に含まれる内容の要旨
µ PD75P3116 5. DIFFERENCES BETWEEN µ PD75P3116 AND µ PD753104, 753106, 753108 The µ PD75P3116 replaces the internal mask ROM in the µ PD753104, 753106, and 753108 with a one-time PROM and features expanded ROM capacity. The µ PD75P3116’s Mk I mode supports the Mk I mode in the µ PD753104, 753106, and 753108 and the µ PD75P3116’s Mk II mode supports the Mk II mode in the µ PD753104, 753106, and 753108. Table 5-1 lists differences between the µ PD75P3116 and the µ PD753104, 753106, and 753108. B
ページ17に含まれる内容の要旨
µ PD75P3116 6. MEMORY CONFIGURATION Figure 6-1. Program Memory Map 76 5 0 0000H MBE RBE Internal reset start address (higher 6 bits) Internal reset start address (lower 8 bits) 0002H MBE RBE INTBT/INT4 start address (higher 6 bits) INTBT/INT4 start address (lower 8 bits) CALLF !faddr instruction 0004H MBE RBE INT0 start address (higher 6 bits) entry address INT0 start address (lower 8 bits) 0006H MBE RBE INT1 start address (higher 6 bits) INT1 start address (lower 8 bits) BRCB !caddr instructio
ページ18に含まれる内容の要旨
µ PD75P3116 Figure 6-2. Data Memory Map Data memory Memory bank 000H General-purpose register area (32 × 4) 01FH 020H 0 256 × 4 (224 × 4) Note Stack area Data area 0FFH static RAM 100H (512 × 4) 256 × 4 (224 × 4) 1DFH 1 1E0H Display data memory (24 × 4) 1F7H 1F8H (8 × 4) 1FFH Not incorporated F80H 128 × 4 15 Peripheral hardware area FFFH Note Memory bank 0 or 1 can be selected as the stack area. Data Sheet U11369EJ3V0DS 18
ページ19に含まれる内容の要旨
µ PD75P3116 7. INSTRUCTION SET (1) Representation and coding formats for operands In the instruction’s operand area, use the following coding format to describe operands corresponding to the instruction’s operand representations (for further details, refer to the RA75X Assembler Package Language User’s Manual (U12385E)). When there are several codes, select and use just one. Codes that consist of uppercase letters and + or – symbols are keywords that should be entered as they are. For immediat
ページ20に含まれる内容の要旨
µ PD75P3116 (2) Operation conventions A: A register; 4-bit accumulator B: B register C: C register D: D register E: E register H: H register L: L register X: X register XA: Register pair (XA); 8-bit accumulator BC: Register pair (BC) DE: Register pair (DE) HL: Register pair (HL) XA’: Expansion register pair (XA’) BC’: Expansion register pair (BC’) DE’: Expansion register pair (DE’) HL’: Expansion register pair (HL’) PC: Program counter SP: Stack pointer CY: Carry flag; bit accumulator PSW: Progr
