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APPLICATION NOTE
SH7211 Group
Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode)
Introduction
This application note describes the operation of the DMAC, and is intended for reference to help in the design of user
software.
Target Device
SH7211
Contents
1. Introduction ....................................................................................................................................... 2
2. Description of Sample Application ........................
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SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) 1. Introduction 1.1 Specification • DMAC channel 0 is used. • Auto-request mode is used as the interrupt source for activating DMA transfer. • Cycle-stealing mode is used as the bus mode. 1.2 Used Module • Direct memory access controller (DMAC channel 0) 1.3 Applicable Conditions • Microcontroller: SH7211 • Operating Frequency: Internal clock 160 MHz Bus clock 40 MHz Peripheral clock 40 MH
ページ3に含まれる内容の要旨
SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) 2. Description of Sample Application In this sample application, the direct memory access controller (DMAC) is set to auto request mode to transfer 512- Kbtyte data stored in the on-chip RAM to another address. 2.1 Operation of Modules Used When a DMA transfer request is made, the DMAC starts to transfer data in accordance with the priority order of channels and continues the transfer operation until the
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SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) In the normal mode of cycle stealing, bus mastership is given to another bus master after each DMA transfer of one transfer unit (byte, word, longword, or 16-byte unit). When a subsequent transfer request occurs, bus mastership is obtained from the other bus master and transfer proceeds for one transfer unit. When that transfer ends, the bus mastership is passed to another bus master. This is repeated unti
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SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) DMAC module RDMATCR_n On-chip Iteration memory DMATCR_n control On-chip RSAR_n peripheral Register module control SAR_n RDAR_n Start-up control DAR_n DMA transfer request signal CHCR_n DMA transfer acknowledge signal Request HEIn priority DMAOR Interrupt controller control DEIn DMARS0 to DMARS3 External ROM Bus interface External RAM External device (memory mapped) Bus state External device contro
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SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) 2.2 Operational Description of Sample Program The settings of the DMAC for the sample program are listed in table 4. Also, the operation of the sample program is illustrated in figure 4. Table 4 Settings of DMAC DMA transfer condition Auto request mode Channel CH0 Length of transfer data 4 bytes Maximum transfer count 128 transfers (128 × data length of 4 bytes = 512-byte data) Address mode Dual addres
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SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) 2.3 Procedure for Setting Modules This section describes the procedure for making initial settings when the DMAC is to be used to transfer data between locations within the on-chip RAM. Auto request mode is used for the transfer requests. By default, the on-chip peripheral modules of this MCU are in module standby mode. Whenever any of these modules is to be used, be sure to take it out of module standby m
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SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) DMAC_init [1] Disable DMA transfer Set the DE (DMA enable) bit to 0 Set DMA channel control register [1] Disable DMA transfer (CHCR_0) [2] Set the DMA transfer source address (SAR_0) Specify the DMA transfer source address Set DMA source address register [2] (SAR_0) [3] Set the DMA transfer destination address (DAR_0) Specify the DMA transfer destination address Set DMA destination address [4] Specify th
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SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) 2.4 Register Settings for Sample Program 2.4.1 Clock Pulse Generator (CPG) The settings of the clock pulse generator for the sample program are described in table 5. Table 5 Settings of Clock Pulse Generator Register Name Address Setting Value Description Frequency control H’FFFE0010 H’1303 CKOEN = “B’1”: output clocks register (FRQCR) STC[1:0] = “B’00”: frequency multiplication ratio of PLL circuit ×
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SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) 2.4.3 Direct Memory Access Controller (DMAC) The settings of DMAC registers for the sample program are described in table 7. Table 7 Settings of DMAC Registers Register Name Address Setting Value Description DMA source address H’FFFE1000 H’FFF81000 Transfer source start address register 0 (SAR) DMA destination address H’FFFE1004 H’FFF82000 Transfer destination start address register 0 (DAR) DMA transfe
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SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) 3. Documents for Reference • Software Manual SH-2A, SH2A-FPU Software Manual The most up-to-date version of this document is available on the Renesas Technology Website. • Hardware Manual SH7211 Group Hardware Manual The most up-to-date version of this document is available on the Renesas Technology Website. REJ06B0732-0100/Rev.1.00 March 2008 Page 11 of 13
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SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) Website and Support Renesas Technology Website http://www.renesas.com/ Inquiries http://www.renesas.com/inquiry csc@renesas.com Revision Record Description Rev. Date Page Summary 1.00 Mar.21.08 — First edition issued All trademarks and registered trademarks are the property of their respective owners. REJ06B0732-0100/Rev.
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SH7211 Group Data Transfer between On-chip RAM Areas with DMAC (Cycle-Stealing Mode) Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or
