ページ1に含まれる内容の要旨
TMS320DM643x DMP
Universal Asynchronous Receiver/Transmitter
(UART)
User's Guide
Literature Number: SPRU997C
December 2009
ページ2に含まれる内容の要旨
2 SPRU997C–December 2009 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
ページ3に含まれる内容の要旨
Preface ....................................................................................................................................... 6 1 Introduction ........................................................................................................................ 7 1.1 Purpose of the Peripheral .............................................................................................. 7 1.2 Features ............................................................................
ページ4に含まれる内容の要旨
www.ti.com List of Figures 1 UART Block Diagram....................................................................................................... 9 2 UART Clock Generation Diagram....................................................................................... 10 3 Relationships Between Data Bit, BCLK, and UART Input Clock.................................................... 11 4 UART Protocol Formats .....................................................................................
ページ5に含まれる内容の要旨
www.ti.com List of Tables 1 UART Supported Features/Characteristics by Instance ............................................................... 8 2 Baud Rate Examples for 27 MHz UART Input Clock................................................................. 11 3 UART Signal Descriptions................................................................................................ 12 4 Character Time for Word Lengths..............................................................................
ページ6に含まれる内容の要旨
Preface SPRU997C–December 2009 Read This First About This Manual This document describes the universal asynchronous receiver/transmitter (UART) peripheral in the TMS320DM643x Digital Media Processor (DMP) . Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown in figures and described in tables. – Each register figure show
ページ7に含まれる内容の要旨
User's Guide SPRU997C–December 2009 Universal Asynchronous Receiver/Transmitter (UART) 1 Introduction This document describes the universal asynchronous receiver/transmitter (UART) peripheral in the TMS320DM643x Digital Media Processor (DMP) . 1.1 Purpose of the Peripheral The UART peripheral is based on the industry standard TL16C550 asynchronous communications element, which in turn is a functional upgrade of the TL16C450. Functionally similar to the TL16C450 on power up (single character or T
ページ8に含まれる内容の要旨
Introduction www.ti.com Table 1 summarizes the capabilities supported on the UART. Note that the number of UARTs and their supported features vary on each device, see the device-specific data manual for more details. Table 1. UART Supported Features/Characteristics by Instance Feature Support 5, 6, 7 or 8-bit characters Supported Even, odd, or no PARITY bit Supported 1, 1.5, or 2 STOP bit generation Supported Line break generation and detection Supported Internal loop back Supported DMA sync eve
ページ9に含まれる内容の要旨
www.ti.com Introduction Figure 1. UART Block Diagram S e 8 8 l Receiver e FIFO 8 c t Receiver 8 RX Shift Data Receiver Peripheral Register pin Bus Bus Buffer Buffer Register 16 Receiver Line Timing and Control Control Register Divisor Latch (LS) 16 Baud Generator Divisor Latch (MS) Transmitter Line Timing and Status Control Register 8 8 Transmitter S FIFO e l e Transmitter Transmitter 8 8 TX c Shift Holding pin t Register Register Modem 8 Control Control Logic Register Interrupt Interrupt/ 8
ページ10に含まれる内容の要旨
Peripheral Architecture www.ti.com 2 Peripheral Architecture 2.1 Clock Generation and Control The UART bit clock is sourced from the PLLC1 AUXCLK. It supports up to 128 kbps maximum data rate. Figure 2 is a conceptual clock generation diagram for the UART. The processor clock generator receives a signal from an external clock source and produces a UART input clock with a programmed frequency. The UART contains a programmable baud generator that takes an input clock and divides it by a divisor in
ページ11に含まれる内容の要旨
www.ti.com Peripheral Architecture Figure 3. Relationships Between Data Bit, BCLK, and UART Input Clock n UART input clock cycles, where n = divisor in DLH:DLL UART input clock n BCLK Each bit lasts 16 BCLK cycles. When receiving, the UART samples the bit in the 8th cycle. BCLK TX, D1 D2 RX D0 TX, START PARITY STOP1 STOP2 D0 D1 D2 D3 D4 D5 D6 D7 RX Table 2. Baud Rate Examples for 27 MHz UART Input Clock Baud Rate Divisor Value Actual Baud Rate Error (%) 2400 703 2400.427 0.018 4800 352 4794.034
ページ12に含まれる内容の要旨
Peripheral Architecture www.ti.com 2.2 Signal Descriptions The UARTs utilize a minimal number of signal connections to interface with external devices. The UART signal descriptions are included in Table 3. Note that the number of UARTs and their supported features vary on each device, see the device-specific data manual for more details. Table 3. UART Signal Descriptions (1) Signal Name Signal Type Function UTXDn Output Serial data transmit URXDn Input Serial data receive UCTSn Input Clear-to-Se
ページ13に含まれる内容の要旨
www.ti.com Peripheral Architecture 2.4.3 Data Format The UART transmits in the following format: 1 START bit + data bits (5, 6, 7, 8) + 1 PARITY bit (optional) + STOP bit (1, 1.5, 2) It transmits 1 START bit; 5, 6, 7, or 8 data bits, depending on the data width selection; 1 PARITY bit, if parity is selected; and 1, 1.5, or 2 STOP bits, depending on the STOP bit selection. The UART receives in the following format: 1 START bit + data bits (5, 6, 7, 8) + 1 PARITY bit (optional) + STOP bit (1) It r
ページ14に含まれる内容の要旨
Peripheral Architecture www.ti.com 2.6 Operation 2.6.1 Transmission The UART transmitter section includes a transmitter hold register (THR) and a transmitter shift register (TSR). When the UART is in the FIFO mode, THR is a 16-byte FIFO. Transmitter section control is a function of the UART line control register (LCR). Based on the settings chosen in LCR, the UART transmitter sends the following to the receiving device: • 1 START bit • 5, 6, 7, or 8 data bits • 1 PARITY bit (optional) • 1, 1.5,
ページ15に含まれる内容の要旨
www.ti.com Peripheral Architecture 2.6.3 FIFO Modes The following two modes can be used for servicing the receiver and transmitter FIFOs: • FIFO interrupt mode. The FIFO is enabled and the associated interrupts are enabled. Interrupts are sent to the CPU to indicate when specific events occur. • FIFO poll mode. The FIFO is enabled but the associated interrupts are disabled. The CPU polls status bits to detect specific events. Because the receiver FIFO and the transmitter FIFO are controlled sepa
ページ16に含まれる内容の要旨
Peripheral Architecture www.ti.com 2.6.3.2 FIFO Poll Mode When the receiver FIFO is enabled in the FIFO control register (FCR) and the receiver interrupts are disabled in the interrupt enable register (IER), the poll mode is selected for the receiver FIFO. Similarly, when the transmitter FIFO is enabled and the transmitter interrupts are disabled, the transmitted FIFO is in the poll mode. In the poll mode, the CPU detects events by checking bits in the line status register (LSR): • The RXFIFOE b
ページ17に含まれる内容の要旨
www.ti.com Peripheral Architecture 2.6.4.1 RTS Behavior RTS data flow control originates in the receiver block (see Figure 1). When the receiver FIFO level reaches a trigger level of 1, 4, 8, or 14 (see Figure 6), RTS is deasserted. The sending UART may send an additional byte after the trigger level is reached (assuming the sending UART has another byte to send), because it may not recognize the deassertion of RTS until after it has begun sending the additional byte. For trigger level 1, 4, and
ページ18に含まれる内容の要旨
Peripheral Architecture www.ti.com 2.7 Reset Considerations 2.7.1 Software Reset Considerations Two bits in the power and emulation management register (PWREMU_MGMT) control resetting the parts of the UART: • The UTRST bit controls resetting the transmitter only. If UTRST = 1, the transmitter is active; if UTRST = 0, the transmitter is in reset. • The URRST bit controls resetting the receiver only. If URRST = 1, the receiver is active; if URRST = 0, the receiver is in reset. In each case, puttin
ページ19に含まれる内容の要旨
www.ti.com Peripheral Architecture Table 5. UART Interrupt Requests Descriptions UART Interrupt Request Interrupt Source Comment THREINT THR-empty condition: The transmitter holding register If THREINT is enabled in IER, by setting the ETBEI (THR) or the transmitter FIFO is empty. All of the data bit, it is recorded in IIR. has been copied from THR to the transmitter shift As an alternative to using THREINT, the CPU can poll register (TSR). the THRE bit in the line status register (LSR). RDAINT
ページ20に含まれる内容の要旨
Peripheral Architecture www.ti.com 2.10 DMA Event Support In the FIFO mode, the UART generates the following two DMA events: • Receive event (URXEVT): The trigger level for the receiver FIFO (1, 4, 8, or 14 characters) is set with the RXFIFTL bit in the FIFO control register (FCR). Every time the trigger level is reached or a receiver time-out occurs, the UART sends a receive event to the EDMA controller. In response, the EDMA controller reads the data from the receiver FIFO by way of the receiv
