ページ1に含まれる内容の要旨
TOSHIBA Original CMOS 32-Bit Microcontroller
TLCS-900/H1 Series
TMP92CM22FG
Semiconductor Company
ページ2に含まれる内容の要旨
Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”.
ページ3に含まれる内容の要旨
TMP92CM22 CMOS 32-Bit Microcontrollers TMP92CM22FG 1. Outline and Device Characteristics TMP92CM22 is high-speed advanced 32-bit microcontroller developed for controlling equipment, which processes mass data. TMP92CM22FG is a microcontroller, which has a high-performance CPU (900/H1 CPU) and various built-in I/Os. TMP92CM22F is housed in a 100-pin flat package. Device characteristics are as follows: (1) CPU: 32-bit CPU (900/H1 CPU) • Compatible with TLCS-900, 900/L, 900/L1, 900/H, a
ページ4に含まれる内容の要旨
TMP92CM22 (4) External memory expansion • Expandable up to 16 Mbytes (Shared program/data area) • Can simultaneously support 8-/16-bit width external data bus ･･･Dynamic data bus sizing • Separate bus system (5) Memory controller • Chip select output: 4 channels (6) 8-bit timers: 4 channels (7) 16-bit timers: 2 channels (8) General-purpose serial interface: 2 channels • UART/synchronous mode • IrDA (9) Serial bus interface: 1 channel 2 • I C bus mode • Clock synchronous mode
ページ5に含まれる内容の要旨
TMP92CM22 PG0 to PG7 DVCC [3] (AN0 to AN7) DVSS [4] PG3 ( ADTRG ) 900/H1 CPU 10-bit 8-ch AVCC AD PLL AVSS converter X1 VREFH H-OSC W A XWA VREFL X2 B C XBC Clock gear PF0 (TXD0) D E XDE Serial I/O PF1 (RXD0) SIO0 H L XHL RESET PF2 (SCLK0/ CTS0 ) Mode AM0 IX controller XIX PF3 (TXD1) AM1 Serial I/O PF4 (RXD1) IY XIY SIO1 NMI Interrupt PF5 (SCLK1/ CTS1 ) IZ controller XIZ PC3(INT0) PF6 to PF7 Port F SP XSP Data bus 32 bits D0 to D7 P90 (SCK) Serial P10 to P17 SR F
ページ6に含まれる内容の要旨
TMP92CM22 2. Pin Assignment and Functions The assignment of input/output pins for the TMP92CM22FG, their names and functions are as follows. 2.1 Pin Assignment Figure 2.1.1 shows the pin assignment of the TMP92CM22FG. VREFL 75 P66/A22 1 VREFH P65/A21 PG0/AN0 P64/A20 PG1/AN1 DVCC3 PG2/AN2 P63/A19 5 PG3/AN3/ ADTRG 70 P62/A18 PG4/AN4 P61/A17 PG5/AN5 P60/A16 PG6/AN6 P57/A15 PG7/AN7 P56/A14 10 TMP92CM22 PA7 65 P55/A13 PC0/TA0IN P54/A12 QFP100 PC1/TA1OUT
ページ7に含まれる内容の要旨
TMP92CM22 2.2 Pin Names and Functions The following tables show the names and functions of the input/output pins. Table 2.2.1 Pin Names and Functions (1/2) Number Pin Names I/O Functions of Pins D0 to D7 8 I/O Data (Lower): Data bus D0 to D7. P10 to P17 I/O Port 1: I/O port that allows I/O to be selected at the bit level. 8 (when used to the external 8-bit bus.) D8 to D15 I/O Data: Data bus D8 to D15. P40 to P47 I/O Port 4: I/O port. 8 A0 to A7 Output Address: Address bus A0
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TMP92CM22 Table 2.2.2 Pin Names and Functions (2/2) Number Pin Names I/O Functions of Pins PC0 I/O Port C0: I/O port. 1 TA0IN Input Timer input: 8-bit timer A0 input. PC1 I/O Port C1: I/O port. INT1 1 Input Interrupt request pin 1: Interrupt request pin with programmable level/rising edge/falling edge. Timer output: 8-bit timer A0 or timer A1 output. TA1OUT Output PC3 I/O Port C3: I/O port. 1 INT0 Input Interrupt request pin 0: Interrupt request pin with programmable level/ris
ページ9に含まれる内容の要旨
TMP92CM22 3. Operation This section describes the basic components, functions and operation of the TMP92CM22. 3.1 CPU The TMP92CM22 incorporates a high-performance 32-bit CPU (The TLCS-900/H1 CPU). For a description of this CPU’s operation, please refer to the section of this data book which describes the TLCS-900/H1 CPU. The following sub-sections describe functions peculiar to the CPU used in the TMP92CM22; these functions are not covered in the section devoted to the TLCS-900/H1 C
ページ10に含まれる内容の要旨
TMP92CM22 3.1.2 Reset Operation When resetting the TMP92CM22 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low for at least 20 system clocks (16 μs at fc = 40 MHz). When the reset has been accepted, the CPU performs the following: • Sets the program counter (PC) as follows in accordance with the reset vector stored at address FFFF00H to FFFF02H:
ページ11に含まれる内容の要旨
TMP92CM22 V 3.3 V CC RESET 0[s] (Min) Oscillator operation time + 20 system clocks Figure 3.1.1 Reset Timing Example 3.1.3 Outline of Operation Mode Set AM1 and AM0 pins to “10” to use 8-bit external bus, or set it to “01” to use 16-bit external bus. Table 3.1.2 Operation Mode Setup Table Mode Setting Input Pin Operation RESET AM1 AM0 16-bit external bus start 0 1 8-/16-bit dynamic bus sizing 8-bit external bus start 1 0 8-/16-bit dynamic bus sizing
ページ12に含まれる内容の要旨
TMP92CM22 3.2 Memory Map Figure 3.2.1 shows memory map of TMP92CM22. 000000H Internal I/O Direct area(n) (8 Kbytes) 000100H 001FE0H 002000H 64-Kbyte area Internal RAM (nn) (32 Kbytes) 00A000H 010000H External memory F00000H Provisinal emulat or control area (64 Kbytes) F10000H External memory 16-Mbyte area (R) ( − R) (R + ) (R + R8/16) (R + d8/16) (nnn) FFFF0
ページ13に含まれる内容の要旨
TMP92CM22 3.3 Clock Function and Standby Function TMP92CM22 contains (1) Clock gear, (2) Standby controller and (3) Noise-reducing circuit. It is used for low-power, low-noise systems. This chapter is organized as follows: 3.3.1 Block Diagram of System Clock 3.3.2 SFRs 3.3.3 System Clock Controller 3.3.4 Clock Doubler (PLL) 3.3.5 Noise Reduction Circuits 3.3.6 Standby Controller 2007-02-16 92CM22-11
ページ14に含まれる内容の要旨
TMP92CM22 The clock operating modes are as follows: (a) Single clock mode (X1 and X2 pins only), (b) Dual clock mode (X1, X2 pins and PLL). Figure 3.3.1 shows a transition figure. Reset (f /32) OSCH Release reset Instruction IDLE2 mode Interrupt Instruction (I/O operation) NORMAL mode STOP mode Instruction Interrupt (Stop all circuit ) (f /gear value/2) IDLE1 mode OSCH Interrupt (Operate only oscillator) (a) Single clock mode transition figure Reset (f /32) OS
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TMP92CM22 3.3.1 Block Diagram of System Clock SYSCR2 PLLCR Warm-up timer (for high-frequency oscillator)/lockup (for PLL) timer φT φT0 f FPH ÷4 ÷8 f = f × 4 PLL OSCH fc fc/2 fc/4 ÷2 f SYS PLLCR fc/8 fc/16 ÷2 f iO PLL (Clock doubler) SYSCR1 ÷2 ÷4 ÷8 ÷16 High- X1 frequency Clock gear X2 oscillator f OSCH PLLCR f CPU SYS TMRA0 to TMRA3 and f iO TMRB0 to TMRB1 RAM φT0 Prescaler Interrupt controller SIO0
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TMP92CM22 3.3.2 SFRs 7 6 5 4 3 2 1 0 SYSCR0 Bit symbol − − (10E0H) Read/Write R/W R/W After reset 1 0 Function Always Always write “1”. write “0”. SYSCR1 Bit symbol − GEAR2 GEAR1 GEAR0 (10E1H) Read/Write R/W After reset 0 1 0 0 Function Always Select gear value of high- write “0”. frequency oscillator 000: High-frequency oscillator 001: High-frequency oscillator/2 010: High-frequency oscillator/4 011: High-frequency oscillator/8 1
ページ17に含まれる内容の要旨
TMP92CM22 7 6 5 4 3 2 1 0 Bit symbol PLLON FCSEL LWUPFG PLLCR (10E8H) Read/Write R/W R After reset 0 0 0 Function 0: PLL 0: fc = PLL warm-up stop OSCH flag 1: PLL 1: fc = 0: Don’t run PLL (× 4) end up or stop 1: End up Note: Logic of PLLCR is different DFM of 900/L1. Figure 3.3.4 SFR for PLL 7 6 5 4 3 2 1 0 Bit symbol PROTECT EXTIN DRVOSCH − EMCCR0 (10E3H) Read/Write R R/W After reset 0 0 1 1 Function Protec
ページ18に含まれる内容の要旨
TMP92CM22 3.3.3 System Clock Controller The system clock controller generates the system clock signal (f ) for the CPU core and SYS internal I/O. It is used as input that fc outputted from high-frequency oscillation circuit and PLL (Clock doubler) SYSCR1, SYSCR1 sets the high-frequency clock gear to either 1, 2, 4, 8, or 16 (fc, fc/2, fc/4, fc/8, or fc/16). These functions can reduce the power consumption of the equipment in which the device is installed. Single clock
ページ19に含まれる内容の要旨
TMP92CM22 3.3.4 Clock Doubler (PLL) PLL outputs the f clock signal, which is four times as fast as f . A reset initializes PLL OSCH PLL to stop status, setting to PLLCR register is needed before use. Like an oscillator, this circuit requires time to stabilize. This is called the lockup time. Note 1: Input frequency limitation for PLL The limitation of input frequency (High-frequency oscillation) for PLL is the following. f = 4 to 10 MHz (Vcc = 3.0 V to 3.6 V) OSCH Note 2: PLLCR
ページ20に含まれる内容の要旨
TMP92CM22 Example 2: PLL stopping PLLCR EQU 10E8H LD (PLLCR), 10XXXXXXB ; Changes fc from 40 MHz to10 MHz. LD (PLLCR), 00XXXXXXB ; Stop PLL. X: Don’t care PLL output: f PLL System clock f SYS Changes from 40 MHz to 10 MHz. Stops PLL operation. Limitation point on the use of PLL 1. When PLL is started, don’t set fc from f to f at same time. OSCH PLL Don’t setting: LD (PLLCR), 00H LD (PLLCR), C0H 2. When PLL is started, don’t set fc from f
