ページ1に含まれる内容の要旨
CY7C1470V25
CY7C1472V25
CY7C1474V25
72-Mbit(2M x 36/4M x 18/1M x 72)
Pipelined SRAM with NoBL™ Architecture
Features Functional Description
• Pin-compatible and functionally equivalent to ZBT™ The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5V,
2M x 36/4M x 18/1M x 72 Synchronous pipelined burst SRAMs
• Supports 250-MHz bus operations with zero wait states
with No Bus Latency™ (NoBL™) logic, respectively. They are
— Available speed grades are 250, 200 and 167 MHz
designed to support unlimited tr
ページ2に含まれる内容の要旨
CY7C1470V25 CY7C1472V25 CY7C1474V25 Logic Block Diagram-CY7C1472V25 (4M x 18) ADDRESS A0, A1, A REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O U U T T P S P D U E A U ADV/LD T N T T WRITE REGISTRY S A R MEMORY E B AND DATA COHERENCY WRITE DQs BWa E ARRAY S U CONTROL LOGIC G DRIVERS A F DQPa T I M F BWb E S DQPb P E E T S R R E I S R N WE S G E E INPUT INPUT E E REGISTER 1 REGISTER 0 OE READ LOGIC CE1 CE2 CE3 Sleep
ページ3に含まれる内容の要旨
CY7C1470V25 CY7C1472V25 CY7C1474V25 Pin Configurations 100-pin TQFP Pinout DQPc 1 NC 1 A DQPb 80 80 DQc 2 NC 2 DQb NC 79 79 DQc 3 DQb NC 3 NC 78 78 V DDQ 4 V 4 V DDQ 77 DDQ V 77 DDQ V 5 V V 5 SS SS V 76 SS SS 76 DQc 6 NC 6 DQb NC 75 75 DQc 7 DQb NC 7 DQPa 74 74 DQc 8 DQb DQb 8 DQa 73 73 DQc 9 DQb DQb 9 DQa 72 72 V V SS 10 V SS SS 10 V 71 SS 71 V V DDQ 11 DDQ V 11 V 70 DDQ 70 DDQ DQc 12 DQb DQb 12 DQa 69 69 DQc 13 DQb DQb 13 DQa 68 68 NC NC 14 V 14 V 67 SS 67 SS V V DD 15 NC DD 15 NC 66 CY7
ページ4に含まれる内容の要旨
CY7C1470V25 CY7C1472V25 CY7C1474V25 Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1470V25 (2M x 36) 1 2 3 4 567 89 10 11 A NC/576M A ADV/LD A A NC CE BW BW CE CEN 1 c b 3 B NC/1G A CE2 CLK WE OE A A NC BW BW d a DQP NC V V V V V V V NC DQP C c DDQ SS SS SS SS SS DDQ b DQ DQ V V V V V V V DQ DQ D c c DDQ DD SS SS SS DD DDQ b b DQ DQ V V V V V V V DQ DQ E c c DDQ DD SS SS SS DD DDQ b b DQ DQ V V V V V V V DQ DQ F c c DDQ DD SS SS SS DD DDQ b b DQ DQ V V V V V V V D
ページ5に含まれる内容の要旨
CY7C1470V25 CY7C1472V25 CY7C1474V25 Pin Configurations (continued) 209-ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1474V25 (1M x 72) 1 2 3 4 56 78 9 10 11 A DQg DQgAA CE ADV/LDA CEA DQb DQb 2 3 B DQg DQg BWS BWS NC WE A BWS BWS DQb DQb c g b f C DQg DQg BWS BWS NC/576M CE NC BWS BWS DQb DQb h d 1 e a D DQg DQg V NC NC/1G OE NC NC V DQb DQb SS SS E DQPg DQPc V V V V V V V DDQ DDQ DD DDQ DDQ DQPf DQPb DD DD DQc F DQc V V V V DQf V NC V SS SS SS SS DQf SS SS G DQc V V DQc V V V DDQ NC DD V DDQ DD DD
ページ6に含まれる内容の要旨
CY7C1470V25 CY7C1472V25 CY7C1474V25 Pin Definitions (continued) Pin Name I/O Type Pin Description ADV/LD Input- Advance/Load Input used to advance the on-chip address counter or load a new address. Synchronous When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. CLK Input- Clock Input. Used to capture all synchronous
ページ7に含まれる内容の要旨
CY7C1470V25 CY7C1472V25 CY7C1474V25 Functional Overview the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst The CY7C1470V25/CY7C1472V25/CY7C1474V25 are cycle. Therefore, the type of access (Read or Write) is synchronous-pipelined Burst NoBL SRAMs designed specifi- maintained throughout the burst sequence. cally to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers contro
ページ8に含まれる内容の要旨
CY7C1470V25 CY7C1472V25 CY7C1474V25 CY7C1474V25, BW for CY7C1470V25 and BW for a,b,c,d a,b Linear Burst Address Table (MODE = GND) CY7C1472V25) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. First Second Third Fourth Address Address Address Address Sleep Mode A1,A0 A1,A0 A1,A0 A1,A0 The ZZ input pin is an asynchronous input. Asserting ZZ 00 01 10 11 places the SRAM in a power conservation “sleep” mode. Two 01 10 11 00 clock cycles are requir
ページ9に含まれる内容の要旨
CY7C1470V25 CY7C1472V25 CY7C1474V25 [1, 2, 3, 8] Partial Write Cycle Description Function (CY7C1470V25) WE BW BW BW BW d c b a Read H X X X X Write – No bytes written L H H H H Write Byte a – (DQ and DQP) L HHH L a a Write Byte b – (DQ and DQP)LHHLH b b Write Bytes b, a L H H L L Write Byte c – (DQ and DQP)LHLHH c c Write Bytes c, a L H L H L Write Bytes c, b L H LL L H Write Bytes c, b, a L H L L L Write Byte d – (DQ and DQP)LLHHH d d Write Bytes d, a L L H H L Write Bytes d, b L LHLH Writ
ページ10に含まれる内容の要旨
CY7C1470V25 CY7C1472V25 CY7C1474V25 Test MODE SELECT (TMS) IEEE 1149.1 Serial Boundary Scan (JTAG) The TMS input is used to give commands to the TAP controller The CY7C1470V25/CY7C1472V25/CY7C1474V25 incorpo- and is sampled on the rising edge of TCK. It is allowable to rates a serial boundary scan test access port (TAP). This port leave this ball unconnected if the TAP is not used. The ball is operates in accordance with IEEE Standard 1149.1-1990 but pulled up internally, resulting in a logic
ページ11に含まれる内容の要旨
CY7C1470V25 CY7C1472V25 CY7C1474V25 Instruction Register Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between Three-bit instructions can be serially loaded into the instruction TDI and TDO. During this state, instructions are shifted register. This register is loaded when it is placed between the through the instruction register through the TDI and TDO balls. TDI and TDO balls as shown in the Tap Controller Block To execute t
ページ12に含まれる内容の要旨
CY7C1470V25 CY7C1472V25 CY7C1474V25 possible to capture all other signals and simply ignore the BYPASS value of the CLK captured in the boundary scan register. When the BYPASS instruction is loaded in the instruction Once the data is captured, it is possible to shift out the data by register and the TAP is placed in a Shift-DR state, the bypass putting the TAP into the Shift-DR state. This places the register is placed between the TDI and TDO balls. The boundary scan register between the TDI a
ページ13に含まれる内容の要旨
CY7C1470V25 CY7C1472V25 CY7C1474V25 2.5V TAP AC Test Conditions 1.8V TAP AC Test Conditions Input pulse levels ................................................ V to 2.5V Input pulse levels..................................... 0.2V to V – 0.2 SS DDQ Input rise and fall time..................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels.........................................1.25V Input t
ページ14に含まれる内容の要旨
CY7C1470V25 CY7C1472V25 CY7C1474V25 Scan Register Sizes Register Name Bit Size (x36) Bit Size (x18) Bit Size (x72) Instruction 333 Bypass 111 ID 32 32 32 Boundary Scan Order–165FBGA 71 52 – Boundary Scan Order–209BGA – – 110 Identification Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant. IDCODE 001 Loads the ID register with the ve
ページ15に含まれる内容の要旨
CY7C1470V25 CY7C1472V25 CY7C1474V25 Boundary Scan Exit Order (2M x 36) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID 1C1 21 R3 41 J11 61 B7 2 D1 22 P2 42 K10 62 B6 3E1 23 R4 43 J10 63 A6 4D2 24 P6 44 H11 64 B5 5E2 25 R6 45 G11 65 A5 6F1 26 R8 46 F11 66 A4 7G1 27 P3 47 E11 67 B4 8F2 28 P4 48 D10 68 B3 9G2 29 P8 49D11 69 A3 10 J1 30 P9 50 C11 70 A2 11 K1 31 P10 51 G10 71 B2 12 L1 32 R9 52 F10 13 J2 33 R10 53 E10 14 M1 34 R11 54 A9 15 N1 35 N11 55 B9 16 K2 36 M11 56 A10
ページ16に含まれる内容の要旨
CY7C1470V25 CY7C1472V25 CY7C1474V25 Boundary Scan Exit Order (1M x 72) Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID 1 A1 29 T1 57 U10 85 B11 2A2 30 T2 58 T11 86 B10 3B1 31 U1 59 T10 87 A11 4B2 32 U2 60 R11 88 A10 5 C1 33 V1 61 R10 89 A7 6C2 34 V2 62 P11 90 A5 7 D1 35 W1 63 P10 91 A9 8D2 36 W2 64 N11 92 U8 9 E1 37 T6 65 N10 93 A6 10 E2 38 V3 66 M11 94 D6 11 F1 39 V4 67 M10 95 K6 12 F2 40 U4 68 L11 96 B6 13 G1 41 W5 69 L10 97 K3 14 G2 42 V6 70 P6 98 A8 15 H1 43 W6 71
ページ17に含まれる内容の要旨
CY7C1470V25 CY7C1472V25 CY7C1474V25 Current into Outputs (LOW)......................................... 20 mA Maximum Ratings Static Discharge Voltage.......................................... > 2001V (Above which the useful life may be impaired. For user guide- (per MIL-STD-883, Method 3015) lines, not tested.) Latch-up Current.................................................... > 200 mA Storage Temperature .................................–65°C to +150°C Operating Range Ambient Temperature
ページ18に含まれる内容の要旨
CY7C1470V25 CY7C1472V25 CY7C1474V25 [14] Capacitance 100 TQFP 165 FBGA 209 FBGA Parameter Description Test Conditions Max. Max. Max. Unit C Address Input Capacitance T = 25°C, f = 1 MHz, 6 6 6 pF ADDRESS A V = 2.5V DD C Data Input Capacitance 5 5 5 pF DATA V = 2.5V DDQ C Control Input Capacitance 8 8 8 pF CTRL C Clock Input Capacitance 6 6 6 pF CLK C Input/Output Capacitance 5 5 5 pF I/O [14] Thermal Resistance 100 TQFP 165 FBGA 209 FBGA Parameter Description Test Conditions Package Packag
ページ19に含まれる内容の要旨
CY7C1470V25 CY7C1472V25 CY7C1474V25 [15, 16] Switching Characteristics Over the Operating Range –250 –200 –167 Parameter Description Min. Max. Min. Max. Min. Max. Unit [17] t V (typical) to the First Access Read or Write 1 1 1 ms Power CC Clock t Clock Cycle Time 4.0 5.0 6.0 ns CYC F Maximum Operating Frequency 250 200 167 MHz MAX t Clock HIGH 2.0 2.0 2.2 ns CH t Clock LOW 2.0 2.0 2.2 ns CL Output Times t Data Output Valid After CLK Rise 3.0 3.0 3.4 ns CO t OE LOW to Output Valid 3.0 3.0 3.4
ページ20に含まれる内容の要旨
CY7C1470V25 CY7C1472V25 CY7C1474V25 Switching Waveforms [21, 22, 23] Read/Write/Timing 123 456789 10 t CYC CLK t t t t CENS CENH CL CH CEN t t CES CEH CE ADV/LD WE BWx A1 A2 ADDRESS A3 A4 A5 A6 A7 t CO t t DS DH t t t t DOH CLZ OEV CHZ t t AS AH Data Q(A4+1) D(A1) D(A2) D(A2+1) Q(A3) Q(A4) D(A5) Q(A6) In-Out (DQ) t OEHZ t DOH t OELZ OE WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D(A1) D(A2) WRITE Q(A3) Q(A4) READ D(A5) Q(A6) D(A7) D(A2+1) Q(A4+1) DON’T CARE UNDEFINED Notes:
