ページ1に含まれる内容の要旨
Dual, Low Noise, Wideband
a
Variable Gain Amplifiers
AD600/AD602*
FEATURES FUNCTIONAL BLOCK DIAGRAM
Two Channels with Independent Gain Control
“Linear in dB” Gain Response GAT1
Two Gain Ranges:
PRECISION PASSIVE
GATING
SCALING
INPUT ATTENUATOR INTERFACE
AD600: 0 dB to +40 dB
REFERENCE
AD602: –10 dB to +30 dB
C1HI
A1OP
V
Accurate Absolute Gain: 60.3 dB G
C1LO
Low Input Noise: 1.4 nV/√Hz
GAIN CONTROL
Low Distortion: –60 dBc THD at 61 V Output
INTERFACE
RF2
2.24kW (AD600)
High Bandwidth: DC to 35 M
ページ2に含まれる内容の要旨
(Each amplifier section, at T = +258C, V = 65 V, –625 mV ≤ V ≤ AD600/AD602–SPECIFICATIONS A S G +625 mV, R = 500 V, and C = 5 pF, unless otherwise noted. Specifications for AD600 and AD602 are identical unless otherwise noted.) L L AD600J/AD602J AD600A/AD602A Parameter Conditions Min Typ Max Min Typ Max Units INPUT CHARACTERISTICS Input Resistance Pins 2 to 3; Pins 6 to 7 98 100 102 95 100 105 Ω Input Capacitance 22 pF 1 Input Noise Spectral Density 1.4 1.4 nV/√Hz Noise Figure R = 50 Ω, Maximum
ページ3に含まれる内容の要旨
AD600/AD602 1 ABSOLUTE MAXIMUM RATINGS PIN DESCRIPTION Supply Voltage ±V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7.5 V S Pin Function Description Input Voltages Pins 1, 8, 9, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V S Pin 1 C1LO CH1 Gain-Control Input “LO” (Positive Pins 2, 3, 6, 7 . . . . . . . . . . . . . . . . . . . . . . . ±2 V Continuous Voltage Reduces CH1 Gain). . . . . . . . . . . . . . . . . . . . . . . . . . ±V fo
ページ4に含まれる内容の要旨
AD600/AD602 THEORY OF OPERATION It will help, in understanding the AD600, to think in terms of a The AD600 and AD602 have the same general design and fea- mechanical means for moving this slider from left to right; in tures. They comprise two fixed gain amplifiers, each preceded fact, it is voltage controlled. The details of the control interface by a voltage-controlled attenuator of 0 dB to 42.14 dB with in- are discussed later. Note that the gain is at all times exactly de- dependent control i
ページ5に含まれる内容の要旨
AD600/AD602 The Gain-Control Interface Common-Mode Rejection The attenuation is controlled through a differential, high imped- A special circuit technique is used to provide rejection of volt- ance (15 MΩ) input, with a scaling factor which is laser ages appearing between input grounds (A1LO and A2LO) and trimmed to 32 dB per volt, that is, 31.25 mV/dB. Each of the output grounds (A1CM and A2CM). This is necessary because two amplifiers has its own control interface. An internal band- of the “op
ページ6に含まれる内容の要旨
AD600/AD602 A1 A2 –40.00dB –41.07dB OUTPUT INPUT –40.00dB –42.14dB 1.07dB 41.07dB 41.07dB 0dB 0dB C1HI C1LO C1HI C1LO V V G1 G2 V = 0.592V V = 1.908V O1 O2 V = 0V C (a) –0.51dB –1.07dB OUTPUT INPUT –0.51dB –41.63dB 41.07dB 40.56dB 41.07dB 40dB 0dB C1HI C1LO C1HI C1LO V V G1 G2 V = 0.592V V = 1.908V O1 O2 V = 1.25V C (b) 0dB 38.93dB OUTPUT INPUT 0dB –2.14dB 41.07dB 41.07dB 41.07dB 80dB 0dB C1HI C1LO C1HI C1LO V V G1 G2 V = 0.592V V = 1.908V O1 O2 V = 25V C (c) Figure
ページ7に含まれる内容の要旨
AD600/AD602 75 90 80 70 70 65 60 60 50 55 40 50 30 COMBINED A1 45 20 A2 40 10 35 0 –10 30 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 V V C C Figure 5. Plot of Separate and Overall Gains in Sequential Figure 8. SNR for Cascaded Stages—Parallel Control Control 5 1.2 4 1.0 3 0.8 2 0.6 1 0.4 0 0.2 –1 0.0 –2 –0.2 –3 –0.4 –4 –0.6 –5 –0.8 –6 –1.0 –7 –8 –1.2 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 V V C C Figure 6. Gain Error for Cas
ページ8に含まれる内容の要旨
AD600/AD602 APPLICATIONS Increasing Output Drive The full potential of any high performance amplifier can only be The AD600/AD602’s output stage has limited capability for realized by careful attention to details in its applications. The negative-load driving capability. For driving loads less than following pages describe fully tested circuits in which many such 500 Ω, the load drive may be increased by about 5 mA by con- details have already been considered. However, as is always true necting
ページ9に含まれる内容の要旨
AD600/AD602 GAIN-CONTROL An inexpensive circuit, using complementary transistor types VOLTAGE chosen for their low r , is shown in Figure 14. The gain is de- V G bb termined by the ratio of the net collector load resistance to the net emitter resistance, that is, it is an open-loop amplifier. The C1LO C1HI 1 16 gain will be X2 (6 dB) only into a 100 Ω load, assumed to be A1HI A1CM 15 2 provided by the input resistance of the X-AMP; R2 and R7 are A1 A1LO A1OP 100W 3 14 in shunt with this load, an
ページ10に含まれる内容の要旨
AD600/AD602 +5V R3 46.4kW +5V R4 3.74kW 300m A V ' +5V G AD590 (at 300K) RF C1LO C1HI FB 1 16 INPUT 0.1m F A1CM A1HI C2 15 2 C4 +5V DEC R1 1m F A1 0.1m F A1LO A1OP 100W Q1 3 14 2N3904 –5V DEC VPOS GAT1 +5V 4 13 C1 DEC 0.1m F REF R2 100pF FB C3 GAT2 VNEG –5V 5 12 V 806W PTAT 15pF DEC 1% A2LO A2OP RF 6 11 –5V OUTPUT A2 A2HI A2CM POWER SUPPLY 7 10 DECOUPLING NETWORK C2HI C2LO 8 9 AD600 Figure 15. This Accurate HF AGC Amplifier Uses Just Three Active Components A simple half-wave detector is used,
ページ11に含まれる内容の要旨
AD600/AD602 +5V The emitter circuit of Q1 is somewhat inductive (due its finite f t and base resistance). Consequently, the effective value of R2 in- 300m A creases with frequency. This would result in an increase in the AD590 (at 300K) stabilized output amplitude at high frequencies, but for the ad- TO AD600 PIN 16 dition of C3, determined experimentally to be 15 pF for the C2 2N3904 for maximum response flatness. Alternatively, a faster 1m F transistor can be used here to reduce HF peaking. Fi
ページ12に含まれる内容の要旨
AD600/AD602 V RMS AF/RF OUTPUT C1 C4 0.1m F 4.7m F +6V INPUT +6V DEC 1V RMS MAX FB C1LO C1HI R1 1 0.1m F 1 14 (SINE WAVE) 16 VINP VPOS 115W U2 A1HI A1CM +6V DEC 2 15 2 13 NC NC AD636 A1 R2 200W A1LO A1OP 3 14 3 VNEG 12 NC –6V DEC –6V DEC GAT1 VPOS 0.1m F 4 13 +6V DEC 4 11 CAVG NC FB R7 REF R3 GAT2 VNEG C2 R6 56.2kW 5 12 –6V DEC 5 10 NC VLOG COMM 133kW 2m F 3.16kW A2LO A2OP –6V 6 11 6 9 NC BFOP LDLO POWER SUPPLY A2 A2HI A2CM DECOUPLING NETWORK 7 10 7 BFIN VRMS 8 U3A C2LO C2HI 8 9 +316.2mV U1 AD60
ページ13に含まれる内容の要旨
AD600/AD602 (This system can, of course, be used as an AGC amplifier, in ±0.5 dB, and within ±1 dB for the 80 dB range from 80 μV to which the rms value of the input is leveled.) Figure 21 shows the 800 mV. By suitable choice of the input attenuator R1 + R2, “decibel” output voltage. More revealing is Figure 22, which this could be centered to cover any range from 25 mV to 250 mV shows that the deviation from the ideal output predicted by to, say, 1 mV to 10 V, with appropriate correction to the
ページ14に含まれる内容の要旨
AD600/AD602 INPUT 1V RMS MAX C1LO C1HI C1LO C1HI 1 1 (SINE WAVE) 16 16 R3 A1HI A1CM A1HI A1CM R2 2 2 15 15 C1 200W C4 487W V A1 A1 A1LO A1LO OUT A1OP 0.1m F U3A A1OP 2m F 3 14 3 14 GAT1 VPOS GAT1 VPOS 4 1/4 4 13 +5V DEC 13 +5V DEC R1 AD713 REF REF GAT2 VNEG GAT2 VNEG 133kW 5 12 –5V DEC 5 12 –5V DEC C2 R5 A2LO A2LO A2OP 6 6 A2OP 11 0.1m F 11 1.58kW A2 A2 A2HI A2CM A2HI A2CM 7 10 7 10 U3B R4 C3 C2LO C2HI C2LO C2HI 8 8 9 9 133kW 220pF 1/4 U1 AD600 U2 AD600 AD713 +5V –2dB +2dB –62.5mV 0dB +62.5mV FB
ページ15に含まれる内容の要旨
AD600/AD602 2.0 The rms value of V is generated at Pin 8 of the AD636; the LOG averaging time for this process is determined by C5, and the 1.5 value shown results in less than 1% rms error at 20 Hz. The slowly varying V rms is compared with a fixed reference of 1.0 316 mV, derived from the positive supply by R10/R11. Any dif- 0.5 ference between these two voltages is integrated in C6, in con- 0.1 junction with op amp U3C, the output of which is V . A LOG 0 –0.1 fraction of this voltage, determi
ページ16に含まれる内容の要旨
AD600/AD602 C1LO C1HI C1LO C1HI 1 1 16 16 A1HI A1CM A1HI A1CM R2 2 15 2 15 C1 C4 100W A1 A1 V A1LO A1LO OUT A1OP 0.1m F U3A A1OP 2m F 3 14 3 14 GAT1 VPOS GAT1 VPOS 1/4 4 13 +6V DEC 4 13 +6V DEC R1 AD713 REF REF GAT2 VNEG GAT2 VNEG 133kW 5 12 –6V DEC 5 12 –6V DEC C2 A2LO A2OP R5 A2LO 6 11 0.1m F 6 11 A2OP 5.36kW A2 A2 A2HI A2HI A2CM A2CM 7 10 7 10 U3B C2HI R4 C3 C2HI C2LO C2LO 8 9 8 9 133kW 0.001m F 1/4 U1 AD600 U2 AD600 AD713 +6V R3 R6 R7 R8 R9 R16 R17 INPUT 200W 3.4kW 1kW 294W 1kW 287W 115W C5
ページ17に含まれる内容の要旨
AD600/AD602 2.0 In contrast, the S/N ratio for the sequential mode is shown in Figure 34. U1A always acts as a fixed noise source; varying its 1.5 gain has no influence on the output noise. (This is a feature of 1.0 the X-AMP technique.) Thus, for the first 40 dB of control range (actually slightly more, as explained below), when only 0.5 this VCA section has its gain varied, the S/N ratio remains con- 0.2 stant. During this time, the gains of U1B and U2A are at their 0 –0.2 minimum value of –1.
ページ18に含まれる内容の要旨
AD600/AD602–Typical Performance Characteristics 0.45 0.35 20dB 10dB 0.25 7dB 17dB 0.15 0.05 0 0 –0.05 –45 –45 –0.15 –90 –90 –0.25 –0.35 –0.45 –0.7 –0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 100k 1M 10M 100M 100k 1M 10M 100M GAIN CONTROL VOLTAGE – Volts FREQUENCY – Hz FREQUENCY – Hz Figure 35. Gain Error vs. Gain Figure 36. AD600 Frequency and Figure 37. AD602 Frequency and Control Voltage Phase Response vs. Gain Phase Response vs. Gain –1.0 10.0 –1.2 V =0V 9.8 G 10dB/DIV –1.4 9.6 CENTER –1.6 FREQ 1M
ページ19に含まれる内容の要旨
AD600/AD602 1V 50mV 50mV 100 100 100 90 90 90 OUTPUT OUTPUT OUTPUT 10 10 10 0% 0% 0% INPUT INPUT 5V 100nS 5V 100nS 100mV 500nS INPUT Figure 44. Gating Feedthrough to Figure 45. Gating Feedthrough to Figure 46. Transient Response, Output, Gating Off to On Output, Gating On to Off Medium and High Gain 500mV 500mV 1V 100 100 100 90 90 90 OUTPUT OUTPUT OUTPUT 10 10 10 0% 0% 0% INPUT INPUT INPUT 200mV 1V 200nS 500nS 1V 500nS Figure 47. Input
ページ20に含まれる内容の要旨
AD600/AD602 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Pin Plastic DIP (N-16) Package 16 9 0.25 0.31 (7.87) (6.35) 18 0.87 (22.1) MAX 0.035 0.18(4.57) (0.89) MAX 0.18 0.125 0.011 (3.18) (4.57) (0.28) MIN 0.3 (7.62) 0.033 (0.84) 0.1 (2.54) 0.018 (0.46) 16-Pin SOIC (R-16) Package 16 9 0.299 0.419 (7.60) (10.65) 1 8 0.413 (10.50) 0.030 0.012 (0.75) (0.3) 0.104 (2.65) 0.042 0.05 (1.27) 0.019 0.013 (1.07) REF (0.49) (0.32) 16-Pin Cerdip (Q-16) Package 0.005 (0.13) MIN 0.080 (2.03) MAX
