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ICX418AKL
Diagonal 8mm (Type 1/2) CCD Image Sensor for NTSC Color Video Cameras
Description
20 pin DIP (Cer-DIP)
The ICX418AKL is an interline CCD solid-state
image sensor suitable for NTSC color video cameras
with a diagonal 8mm (Type 1/2) system. Compared
with the current product ICX038DNA, basic
characteristics such as sensitivity, smear, dynamic
range and S/N are improved drastically.
This chip features a field period readout system and
an electronic shutter with variable charge-storage
time
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ICX418AKL USE RESTRICTION NOTICE (December 1, 2003 ver.) This USE RESTRICTION NOTICE ("Notice") is for customers who are considering or currently using the CCD products ("Products") set forth in this specifications book. Sony Corporation ("Sony") may, at any time, modify this Notice which will be available to you in the latest specifications book for the Products. You should abide by the latest version of this Notice. If a Sony subsidiary or distributor has its own use restriction notice on the
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ICX418AKL Block Diagram and Pin Configuration (Top View) 10 9 8 7 6 5 4 3 2 1 Cy Ye Cy Ye Mg G Mg G Cy Ye Cy Ye G Mg G Mg Cy Ye Cy Ye Mg G Mg G Note) Horizontal Register Note) : Photo sensor 11 12 13 14 15 16 17 18 19 20 Pin Description Pin No. Symbol Description Pin No. Symbol Description 1 Vφ4 Vertical register transfer clock 11 NC 2 Vφ3 Vertical register transfer clock 12 VDSUB Substrate bias circuit supply voltage 3 Vφ2 Vertical register transfer clock 13 NC 4 φSUB Substrate clock 14
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ICX418AKL Absolute Maximum Ratings Item Ratings Unit Remarks Substrate clock φSUB – GND –0.3 to +50 V VDD, VRD, VDSUB, VOUT – GND –0.3 to +18 V Supply voltage VDD, VRD, VDSUB, VOUT – φSUB –55 to +10 V Vφ1, Vφ2, Vφ3, Vφ4 – GND –15 to +20 V Clock input voltage Vφ1, Vφ2, Vφ3, Vφ4 – φSUB to +10 V ∗1 Voltage difference between vertical clock input pins to +15 V Voltage difference between horizontal clock input pins to +17 V Hφ1, Hφ2 – Vφ4 –17 to +17 V φRG – GND –10 to +15 V φRG – φ
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ICX418AKL Bias Conditions 1 [when used in substrate bias internal generation mode] Item Symbol Min. Typ. Max. Unit Remarks Output circuit supply voltage VDD 14.55 15.0 15.45 V Reset drain voltage VRD 14.55 15.0 15.45 V VRD = VDD ∗1 Protective transistor bias VL Substrate bias circuit supply voltage VDSUB 14.55 15.45 V 15.0 ∗2 Substrate clock φSUB ∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL power supply for the V driver should be
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ICX418AKL Clock Voltage Conditions Waveform Item Symbol Min. Typ. Max. Unit Remarks diagram Readout clock voltage VVT 14.55 15.0 15.45 V 1 VVH1, VVH2 –0.05 0 0.05 V VVH = (VVH1 + VVH2)/2 2 VVH3, VVH4 –0.2 0 0.05 V 2 VVL1, VVL2, –9.6 –9.0 –8.5 V VVL = (VVL3 + VVL4)/2 2 VVL3, VVL4 VφV 8.3 9.0 9.65 Vp-p VφV = VVHn – VVLn (n = 1 to 4) 2 | VVH1 – VVH2 | 0.1 V 2 Vertical transfer clock voltage VVH3 – VVH –0.25 0.1 V 2 VVH4 – VVH –0.25 0.1 V 2 VVHH 0.5 V High-level coupling 2 VVHL 0.5 V High-level coup
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ICX418AKL Clock Equivalent Circuit Constant Item Symbol Min. Typ. Max. Unit Remarks CφV1, CφV3 2700 pF Capacitance between vertical transfer clock and GND CφV2, CφV4 2700 pF CφV12, CφV34 820 pF Capacitance between vertical transfer clocks CφV23, CφV41 330 pF CφH1 100 pF Capacitance between horizontal transfer clock and GND CφH2 91 pF CφHH 47 pF Capacitance between horizontal transfer clocks Capacitance between reset gate clock and GND CφRG 11 pF Capacitance between substrate clock and GND CφSUB
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ICX418AKL Drive Clock Waveform Conditions (1) Readout clock waveform 100% VVT 90% φM φM 2 10% 0% 0V tr twh tf (2) Vertical transfer clock waveform Vφ1 Vφ3 VVH1 VVHH VVHH VVH VVHH VVH VVHH VVHL VVHL VVHL VVHL VVH3 VVL1 VVL3 VVLH VVLH VVLL VVLL VVL VVL Vφ2 Vφ4 VVHH VVHH VVHH VVHH VVH VVH VVHL VVHL VVHL VVHL VVH2 VVH4 VVLH VVLH VVL2 VVLL VVLL VVL4 VVL VVL VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4) – 8 –
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ICX418AKL (3) Horizontal transfer clock waveform tr twh tf 90% VφH twl 10% VHL tr twh tf (4) Reset gate clock waveform VRGH twl VφRG Point A RG waveform VRGL + 0.5V VRGLH VRGL VRGLL VRGLm Hφ1 waveform +2.5V VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the
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ICX418AKL Clock Switching Characteristics twh twl tr tf Symbol Item Unit Remarks Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Readout clock VT 2.3 2.5 0.5 0.5 µs During readout Vertical transfer Vφ1, Vφ2, ∗1 15 250 ns clock Vφ3, Vφ4 During ∗2 Hφ 20 20 15 19 15 19 ns imaging During 5.38 0.01 0.01 Hφ1 µs parallel-serial 5.38 0.01 0.01 Hφ2 conversion 11 13 3 3 ns Reset gate clock φRG 51 When draining Substrate clock φSUB 1.5 1.8 0.5 0.5 µs charge ∗1 When vertical transfer clock drive
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ICX418AKL Image Sensor Characteristics (Ta = 25°C) Measurement Item Symbol Min. Typ. Max. Unit Remarks method Sensitivity S 1040 1300 mV 1 Saturation signal Ysat 1000 mV 2 Ta = 60°C Smear Sm –115 –105 dB 3 20 % 4 Zone 0 and I SHy Video signal shading 25 % 4 Zone 0 to II' ∆ Sr 10 % 5 Uniformity between video signal channels ∆ Sb 10 % 5 Ydt 2 mV 6 Ta = 60°C Dark signal ∆ Ydt 1 mV 7 Ta = 60°C Dark signal shading 2 % 8 Flicker Y Fy 5 % 8 Flicker R-Y Fcr Flicker B-Y Fcb 5 % 8 Line crawl R Lcr 3 % 9 L
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ICX418AKL Image Sensor Characteristics Measurement Method Measurement conditions 1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions. (when used with substrate bias external adjustment, set the substrate voltage to the value indicated on the device.) 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (OB) is used as the reference for the signal outp
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ICX418AKL Definition of standard imaging conditions 1) Standard imaging condition I: 2 Use a pattern box (luminance 706cd/m , color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) Standard imaging condition II: Image a
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ICX418AKL 7. Dark signal shading After measuring 6, measure the maximum (Ydmax [mV]) and minimum (Ydmin [mV]) values of the dark signal output and substitute the values into the following formula. ∆ Ydt = Ydmax – Ydmin [mV] 8. Flicker 1) Fy Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal output is 200mV, and then measure the difference in the signal level between fields (∆ Yf [mV]). Then substitute the value into the following formula
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Hφ2 Vφ4 Hφ1 Vφ3 NC Vφ2 φRG φSUB RD GND GND Vφ1 GND VL NC GND VDSUB VDD VOUT NC ICX418AKL – 15 – Drive Circuit 1 (substrate bias internal generation mode) 15V 1 20 100k 2 19 3 18 1/35V 1 4 17 XSUB XV2 5 16 –9V CXD1267AN 3.3/16V XV1 6 15 XSG1 7 14 22/16V 1M 8 13 XV3 9 12 XSG2 10 11 XV4 22/20V 0.01 3.3/20V 1 2 3 4 5 6 7 8 9 10 ICX418 (BOTTOM VIEW) 20 19 18 17 16 15 14 13 12 11 Hφ1 0.01 Hφ2 100 ∗ [ A] CCD OUT 3.9k 0.01 RG
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Hφ2 Vφ4 Hφ1 Vφ3 NC Vφ2 φRG φSUB RD GND GND Vφ1 GND VL NC GND VDSUB VDD NC VOUT ICX418AKL – 16 – Drive Circuit 2 (substrate bias external adjustment mode) 15V 270k 0.1 15k 1 20 47k 56k 2 19 1/35V 15k 1/35V 100k 27k 39k 0.1 3 18 1/35V 0.1 XSUB 4 17 –9V XV2 5 16 CXD1267AN 3.3/16V 6 15 XV1 7 14 XSG1 22/16V 1M 8 13 XV3 9 12 XSG2 XV4 10 11 22/20V 3.3/20V 0.01 1 2 3 4 5 6 7 8 9 10 ICX418 (BOTTOM VIEW) 20 19 18 17 16 15 14 13 12 11 Hφ1 0.01 Hφ2 100 ∗ [ A] CCD OUT 3.9k 0.01 RG
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ICX418AKL Spectral Sensitivity Characteristics (Excludes lens characteristics and light source characteristics) 1.0 Cy Ye 0.8 G 0.6 0.4 Mg 0.2 0 400 450 500 550 600 650 700 Wave Length [nm] Sensor Readout Clock Timing Chart V1 2.5 V2 Odd Field V3 V4 1.6 2.5 2.5 2.5 33.5 0.2 V1 V2 Even Field V3 V4 Unit: µs – 17 – Relative Response
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520 525 1 2 3 4 5 10 15 20 260 265 270 275 280 ICX418AKL – 18 – Drive Timing Chart (Vertical Sync) FLD VD BLK HD V1 V2 V3 V4 493 24 6 1 3 5 24 6 494 1 3 5 CCD 2 4 6 494 13 5 13 5 493 2 4 6 OUT
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760 768 1 2 3 5 10 20 30 40 1 2 3 5 10 20 22 1 2 3 1 2 3 10 20 ICX418AKL – 19 – Drive Timing Chart (Horizontal Sync) HD BLK H1 H2 RG V1 V2 V3 V4 SUB
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ICX418AKL Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CC
