Summary of the content on the page No. 1
CY7C67200
EZ-OTG™ Programmable USB
On-The-Go
EZ-OTG Features
• Single-chip programmable USB dual-role (Host/Peripheral) • SPI supports both master and slave
controller with two configurable Serial Interface Engines
• Supports 12 MHz external crystal or clock
(SIEs) and two USB ports
• 2.7V to 3.6V power supply voltage
• Supports USB OTG protocol
• Package option: 48-pin FBGA
• On-chip 48-MHz 16-bit processor with dynamically
switchable clock speed
Typical Applications
• Configurable IO block
Summary of the content on the page No. 2
CY7C67200 Interrupts Introduction EZ-OTG provides 128 interrupt vectors. The first 48 vectors EZ-OTG™ (CY7C67200) is Cypress Semiconductor’s first are hardware interrupts and the following 80 vectors are USB On-The-Go (OTG) host/peripheral controller. EZ-OTG is software interrupts. designed to easily interface to most high-performance CPUs to add USB host functionality. EZ-OTG has its own 16-bit RISC General Timers and Watchdog Timer processor to act as a coprocessor or operate in standalone E
Summary of the content on the page No. 3
CY7C67200 USB Interface OTG Interface EZ-OTG has two built-in Host/Peripheral SIEs that each have EZ-OTG has one USB port that is compatible with the USB a single USB transceiver, meeting the USB 2.0 specification On-The-Go supplement to the USB 2.0 specification. The USB requirements for full and low speed (high speed is not support- OTG port has various hardware features to support Session ed). In Host mode, EZ-OTG supports two downstream ports; Request Protocol (SRP) and Host Negotiation Pr
Summary of the content on the page No. 4
CY7C67200 UART Features • Individual bit transfer for non-byte aligned serial communi- cation in PIO mode • Supports baud rates of 900 to 115.2K • Programmable delay timing for the active/inactive master •8-N-1 SPI clock UART Pins • Auto or manual control for master mode slave select signal • Complete access to internal memory Table 5. UART Interface Pins Pin Name Pin Number SPI Pins TX B5 The SPI port has a few different pin location options as shown in Table 7. The pin location is selectabl
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CY7C67200 [1, 2] Host Port Interface (HPI) Table 9. HPI Interface Pins (continued) EZ-OTG has an HPI interface. The HPI interface provides Pin Name Pin Number DMA access to the EZ-OTG internal memory by an external D7 B5 host, plus a bidirectional mailbox register for supporting D6 B4 high-level communication protocols. This port is designed to be the primary high-speed connection to a host processor. D5 C4 Complete control of EZ-OTG can be accomplished through D4 B3 this interface via an ex
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CY7C67200 Charge Pump Features Figure 3. Power Supply Connection Without Booster • Meets OTG Supplement Requirements, see Table 41, “DC Characteristics: Charge Pump,” on page 66. BOOSTVcc 3.0V to 3.6V Charge Pump Pins Power Supply Table 11.Charge Pump Interface Pins Pin Name Pin Number VSWITCH OTGVBUS C1 CSwitchA D1 CSwitchB D2 VCC Booster Interface AVCC EZ-OTG has an on-chip power booster circuit for use with power supplies that range between 2.7V and 3.6V. The booster circuit b
Summary of the content on the page No. 7
CY7C67200 Crystal Pins Operational Modes There are two modes of operation: Coprocessor and Table 13.Crystal Pins Standalone. Pin Name Pin Number Coprocessor Mode XTALIN G3 EZ-OTG can act as a coprocessor to an external host XTALOUT G2 processor. In this mode, an external host processor drives EZ-OTG and is the main processor rather then EZ-OTG’s own Boot Configuration Interface 16-bit internal CPU. An external host processor may interface EZ-OTG can boot into any one of four modes. The mode it
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CY7C67200 Minimum Hardware Requirements for Standalone Mode – Peripheral Only Figure 5. Minimum Standalone Hardware Configuration – Peripheral Only EZ-OTG CY7C67200 Reset VReg VCC, AVCC, nRESET Logic BoostVCC VBus D+ DPlus Standard-B DMinus D- or Mini-B GND SHIELD Bootstrap Options Vcc Vcc 10k 10k GPIO[30] SCL* GPIO[31] SDA* Int. 16k x8 Code / Data Bootloading Firmware VCC A0 Up to 64k x8 VCC EEPROM A1 WP A2 SCL Reserved 22pf GND SDA XIN GND, AGND, 12MHz BoostGND XOUT 22pf * Parallel Resonan
Summary of the content on the page No. 9
CY7C67200 External (Remote) Wakeup Source registers, USB control registers, the stack, and other BIOS variables. The upper internal memory space contains EZ-OTG There are several possible events available to wake EZ-OTG control registers from 0xC000 to 0xC0FF and the BIOS ROM from Sleep mode as shown in Table 15. These may also be itself from 0xE000 to 0xFFFF. For more information on the used as remote wakeup options for USB applications. See reserved lower memory or the BIOS ROM, refer to the
Summary of the content on the page No. 10
CY7C67200 Registers Table 16.Processor Control Registers Some registers have different functions for a read vs. a write Register Name Address R/W access or USB host vs. USB device mode. Therefore, CPU Flags Register 0xC000 R registers of this type have multiple definitions for the same address. Register Bank Register 0xC002 R/W The default register values listed in this data sheet may be Hardware Revision Register 0xC004 R altered to some other value during BIOS initialization. Refer to CPU Sp
Summary of the content on the page No. 11
CY7C67200 Bank Register [0xC002] [R/W] Figure 8. Bank Register Bit # 15 14 13 12 11 10 9 8 Field Address... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 1 Bit # 7 6 5 4 3 2 1 0 Field ...Address Reserved Read/Write R/W R/W R/W - - - - - Default 0 0 0 X X X X X . Register Description Table 17.Bank Register Example The Bank register maps registers R0–R15 into RAM. The Register Hex Value Binary Value eleven MSBs of this register are used as a base address for Bank 0x0100 000
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CY7C67200 CPU Speed Register [0xC008] [R/W] Figure 10. CPU Speed Register Bit # 15 14 13 12 11 10 9 8 Field Reserved... Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Reserved CPU Speed Read/Write - - - - R/W R/W R/W R/W Default 0 0 0 0 1 1 1 1 Register Description The CPU Speed register allows the processor to operate at a user selected speed. This register only affects the CPU; all other peripheral timing is still based on the 48-MHz system clock (unless o
Summary of the content on the page No. 13
CY7C67200 Power Control Register [0xC00A] [R/W] Figure 11. Power Control Register Bit # 15 14 13 12 11 10 9 8 Reserved Host/Device 2 Reserved Host/Device 1 OTG Reserved HSS SPI Field Wake Enable Wake Enable Wake Enable Wake Enable Wake Enable Read/Write - R/W - R/W R/W - R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 HPI Reserved GPI Reserved Boost 3V Sleep Halt Field Wake Enable Wake Enable OK Enable Enable Read/Write R/W - - R/W - R R/W R/W Default 0 0 0 0 0 0 0 0 Register Descriptio
Summary of the content on the page No. 14
CY7C67200 Halt Enable (Bit 0) immediately following the HALT instruction may be executed before the waking interrupt is serviced (you may want to follow Setting this bit to ‘1’ immediately initiates HALT mode. While the HALT instruction with two NOPs). in HALT mode, only the CPU is stopped. The internal clock still runs and all peripherals still operate, including the USB 1: Enable Halt Mode engines. The power savings using HALT in most cases will be 0: No Function minimal, but in applications
Summary of the content on the page No. 15
CY7C67200 UART Interrupt Enable (Bit 3) Timer 1 Interrupt Enable (Bit 1) The UART Interrupt Enable bit enables or disables the The Timer 1 Interrupt Enable bit enables or disables the following UART hardware interrupts: UART TX and UART RX. TImer1 Interrupt Enable. When this bit is reset, all pending Timer 1 interrupts are cleared. 1: Enable UART interrupt 1: Enable TM1 interrupt 0: Disable UART interrupt 0: Disable TM1 interrupt GPIO Interrupt Enable (Bit 2) Timer 0 Interrupt Enable (Bit 0) T
Summary of the content on the page No. 16
CY7C67200 USB Diagnostic Register [0xC03C] [R/W] Figure 14. USB Diagnostic Register Bit # 15 14 13 12 11 10 9 8 Reserved Port 2A Reserved Port 1A Reserved... Diagnostic Diagnostic Field Enable Enable Read/Write - R/W - R/W - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 ...Reserved Pull-down LS Pull-up FS Pull-up Reserved Force Select Field Enable Enable Enable Read/Write - R/W R/W R/W - R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register Description FS Pull-up Enable (Bit 4) The USB Diagnosti
Summary of the content on the page No. 17
CY7C67200 Watchdog Timer Register [0xC00C] [R/W] Figure 15. Watchdog Timer Register Bit # 15 14 13 12 11 10 9 8 Field Reserved... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 ...Reserved Timeout Period Lock WDT Reset Field Flag Select Enable Enable Strobe Read/Write R/W R/W R/W R/W R/W R/W R/W W Default 0 0 0 0 0 0 0 0 Register Description Lock Enable (Bit 2) The Watchdog Timer register provides status and control over The Lock Enable bit does not a
Summary of the content on the page No. 18
CY7C67200 Timer n Register [R/W] • Timer 0 Register 0xC010 • Timer 1 Register 0xC012 Figure 16. Timer n Register Bit # 15 14 13 12 11 10 9 8 Field Count... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1 Bit # 7 6 5 4 3 2 1 0 Field ...Count Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1 Register Description The Timer n Register sets the Timer n count. Both Timer 0 and Timer 1 decrement by one every 1-µs clock tick. Each can provide an interrupt to the CP
Summary of the content on the page No. 19
CY7C67200 Port A D+ Status (Bit 13) Table 24.Port A Force D± State The Port A D+ Status bit is a read-only bit that indicates the Port A Force D± State value of DATA+ on Port A. Function MSB LSB 1: D+ is high 0 0 Normal Operation 0: D+ is low 0 1 Force USB Reset, SE0 State Port A D– Status (Bit 12) 1 0 Force J-State The Port A D– Status bit is a read-only bit that indicates the 1 1 Force K-State value of DATA– on Port A. Suspend Enable (Bit 2) 1: D– is high The Suspend Enable bit enables or di
Summary of the content on the page No. 20
CY7C67200 Host n Control Register [R/W] • Host 1 Control Register 0xC080 • Host 2 Control Register 0xC0A0 Figure 18. Host n Control Register Bit # 15 14 13 12 11 10 9 8 Field Reserved Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Preamble Sequence Sync ISO Reserved Arm Field Enable Select Enable Enable Enable Read/Write R/W R/W R/W R/W - - - R/W Default 0 0 0 0 0 0 0 0 Register Description 1: The next enabled packet will be transferred after the SOF or EOP packet is
