Summary of the content on the page No. 1
STK17TA8
128k X 8 AutoStore™ nvSRAM
with Real Time Clock
Features Description
■ nvSRAM Combined with Integrated Real Time Clock Functions The Cypress STK17TA8 combines a 1 Mb nonvolatile static RAM
(RTC, Watchdog Timer, Clock Alarm, Power Monitor) (nvSRAM) with a full featured real time clock in a reliable,
monolithic integrated circuit.
■ Capacitor or Battery Backup for RTC
The 1 Mb nvSRAM is a fast static RAM with a nonvolatile
■ 25, 45 ns Read Access and Read/Write Cycle Time
Quantum Trap sto
Summary of the content on the page No. 2
STK17TA8 Pinouts Figure 1. Pin Diagram - 48-PIn SSOP [1] Relative PCB Area Usage V CAP 1 48 VCC A 16 A15 2 47 A 14 3 46 HSB A 12 4 45 W A 7 A 5 44 13 A A 6 43 8 6 A5 A9 7 42 INT 41 NC 8 A A 4 9 40 11 NC 39 NC 10 (TOP) NC 11 38 NC NC 37 12 NC V SS 13 36 V SS 35 NC 14 NC V RTCbat 34 VRTCcap 15 DQ0 DQ 16 33 6 A 3 32 G 17 A2 A 18 31 10 A 30 E 1 19 A 20 29 DQ7 0 DQ1 28 DQ 21 5 DQ 2 DQ 22 27 4 X DQ 1 23 26 3 X V 2 24 CC 25 Pin Descriptions Pin Name IO Type Description A -A Input Address: The 17 addr
Summary of the content on the page No. 3
STK17TA8 RF (SSOP-48) Package Thermal Characteristics Absolute Maximum Ratings θ 6.2 C/W; θ 51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm] jc ja Voltage on Input Relative to Ground ................–0.1V to 4.1V Voltage on Input Relative to V .........–0.5V to (V + 0.5V) SS CC Note: Stresses greater than those listed under “Absolute Voltage on DQ or HSB.....................–0.5V to (V + 0.5V) 0-7 CC Maximum Ratings” may cause permanent damage to the device. Temperature under Bias ................
Summary of the content on the page No. 4
STK17TA8 DC Electrical Characteristics (continued) (V = 2.7V-3.6V) CC Commercial Industrial Units Notes Symbol Parameter Min Max Min Max T Operating Temperature 0 70 –40 85 °C A V Operating Voltage 2.7 3.6 2.7 3.6 V 3.0V +20%, -10% CC V Storage Capacitance 17 57 17 57 μF Between V pin and V , 5V CAP CAP SS rated. NV Nonvolatile STORE operations 200 200 K C DATA Data Retention 20 20 Years At 55 °C R AC Test Conditions Input Pulse Levels ....................................................0V to
Summary of the content on the page No. 5
STK17TA8 RTC DC Characteristics Commercial Industrial Symbol Parameter Units Notes Min Max Min Max I RTC Backup Current — 300 — 350 nA From either V or V BAK RTCcap RTCbat VRTCbat RTC Battery Pin Voltage 1.8 3.3 1.8 3.3 V Typical = 3.0 Volts during normal operation VRTCcap RTC Capacitor Pin Voltage 1.2 2.7 1.2 2.7 V Typical = 2.4 Volts during normal operation tOSCS RTC Oscillator time to start — 10 — 10 sec At MIN Temperature from Power up or Enable —5— 5 sec At 25°C from Power up or Enable
Summary of the content on the page No. 6
STK17TA8 SRAM READ Cycles #1 and #2 Symbols STK17TA8-25 STK17TA8-45 NO. Parameter Units #1 #2 Alt. Min Max Min Max 1t t Chip Enable Access Time 25 45 ns ELQV ACS [3] [3] 2t t t Read Cycle Time 25 45 ns AVAV ELEH RC [4] [4] 3t t t Address Access Time 25 45 ns AVQV AVQV AA 4t t Output Enable to Data Valid 12 20 ns GLQV OE [4] [4] 5t t t Output Hold after Address Change 3 3 ns AXQX AXQX OH 6t t Address Change or Chip Enable to Output Active 3 3 ns ELQX LZ [5] 7t t Address Change or Chip Disable to
Summary of the content on the page No. 7
STK17TA8 SRAM WRITE Cycles #1 and #2 Symbols STK17TA8-25 STK17TA8-45 NO. Parameter Units #1 #2 Alt. Min Max Min Max 11 t t t Write Cycle Time 25 45 ns AVAV AVAV WC 13 t t t Write Pulse Width 20 30 ns WLWH WLEH WP 14 t t t Chip Enable to End of Write 20 30 ns ELWH ELEH CW 15 t t t Data Set-up to End of Write 10 15 ns DVWH DVEH DW 16 t t t Data Hold after End of Write 0 0 ns WHDX EHDX DH 17 t t t Address Set-up to End of Write 20 30 ns AVWH AVEH AW 18 t t t Address Set-up to Start of Write 0 0 ns
Summary of the content on the page No. 8
STK17TA8 AutoStore/Power Up Recall Symbols STK17TA8 NO. Parameter Units Notes Standard Alternate Min Max 22 t Power-up RECALL Duration 40 ms 9 HRECALL 23 t t STORE Cycle Duration 12.5 ms 10,11 STORE HLHZ 24 V Low Voltage Trigger Level 2.65 V SWITCH 25 V V Rise Time 150 μS CCRISE CC Figure 9. AutoStore/Power Up RECALL 25 23 23 22 22 NOTE: Read and Write cycles will be ignored during STORE, RECALL and while V is below V CC SWITCH Notes 9. t starts from the time V rises above V HRECALL CC SWITCH
Summary of the content on the page No. 9
STK17TA8 Software-Controlled STORE/RECALL Cycle [12, 13] In the following table, the software controlled STORE and RECALL cycle parameters are listed. Symbols STK17TA8-35 STK17TA8-45 NO. Parameter Units Notes E Cont G Cont Alternate Min Max Min Max 26 t t t STORE / RECALL Initiation Cycle 25 45 ns 13 AVAV AVAV RC Time 27 t t tAS Address Set-up Time 0 0 ns AVEL AVGL 28 t t tCW Clock Pulse Width 20 30 ns ELEH GLGH 29 t t Address Hold Time 1 1 ns EHAX GHAX 30 t t RECALL Duration 100 100 μs RECALL
Summary of the content on the page No. 10
STK17TA8 Hardware STORE Cycle Symbols STK17TA8 NO. Parameter Units Notes Standard Alternate Min Max 31 t t Hardware STORE to SRAM Disabled 1 70 μs14 DELAY HLQZ 32 t Hardware STORE Pulse Width 15 ns HLHX Figure 12. Hardware STORE Cycle 32 23 31 Soft Sequence Commands NO. Symbols Parameter STK17TA8 Units Notes Standard Min Max 33 t Soft Sequence Processing Time 70 μs 15,16 SS Figure 13. Soft Sequence Commands 33 33 Notes 14. On a hardware STORE initiation, SRAM operation continues to be enabled
Summary of the content on the page No. 11
STK17TA8 MODE Selection E W G A -A Mode I/O Power Notes 16 0 H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0x04E38 Read SRAM Output Data 0x0B1C7 Read SRAM Output Data 0x083E0 Read SRAM Output Data Active 17, 18, 19 0x07C1F Read SRAM Output Data 0x0703F Read SRAM Output Data 0x08FC0 Nonvolatile Store Output High Z I CC2 L H L 0x04E38 Read SRAM Output Data Active 0x0B1C7 Read SRAM Output Data 0x083E0 Read SRAM Output Dat
Summary of the content on the page No. 12
STK17TA8 (activated by HSB), Software Store (activated by an address nvSRAM Operation sequence), and AutoStore (on power down). The STK17TA8 nvSRAM is made up of two functional compo- AutoStore operation, a unique feature of Cypress QuanumTrap nents paired in the same physical cell. These are the SRAM technology is a standard feature on the STK17TA8. memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates like a standard fast static RAM. Data in the During normal operation
Summary of the content on the page No. 13
STK17TA8 atile elements. Once a STORE cycle is initiated, further memory Preventing AutoStore inputs and outputs are disabled until the cycle is completed. Because of the use of nvSRAM to store critical RTC data, the To initiate the Software STORE cycle, the following read AutoStore function cannot be disabled on the STK17TA8. sequence must be performed: Best Practices 1. Read Address 0x4E38 Valid READ nvSRAM products have been used effectively for over 15 years. 2. Read Address 0xB1C7 Valid RE
Summary of the content on the page No. 14
STK17TA8 Figure 15. Current versus Cycle Time You can power the real time clock with either a capacitor or a battery. Factors to be considered when choosing a backup power source include the expected duration of power outages and the cost and reliability trade-off of using a battery versus a capacitor. If you select a capacitor power source, connect the capacitor to the V pin and leave the V pin unconnected. RTCcap RTCbat Capacitor backup time values based on maximum current specs are shown be
Summary of the content on the page No. 15
STK17TA8 The alarm value should be initialized on power-up by software Calibrating The Clock since the alarm registers are not nonvolatile. The RTC is driven by a quartz controlled oscillator with a nominal To set or clear Alarm registers, set the write bit “W” (in the Flags frequency of 32.768 KHz. Clock accuracy will depend on the register at 0x1FFF0) to a "1" to enable writes to the Alarm quality of the crystal, specified (usually 35 ppm at 25 C). This registers. Write an alarm value to the
Summary of the content on the page No. 16
STK17TA8 Power Fail Interrupt Enable (PFE). When set to 1, the INT pin is Interrupts driven by a power fail signal from the power monitor circuit. When The STK17TA8 has a Flags register, Interrupt Register, and set to 0, only the PF flag is set. interrupt logic that can interrupt a microcontroller or generate a High/Low (H/L). When set to a 1, the INT pin is active high and power-up master reset signal. There are three potential interrupt the driver mode is push-pull. The INT pin can drive high
Summary of the content on the page No. 17
STK17TA8 RTC Register BCD Format Data Register Function / Range D7 D6 D5 D4 D3 D2 D1 D0 0x1FFFF 10s Years Years Years: 00-99 0x1FFFE 0 0 0 10s Months Months: 01-12 Months 0x1FFFD 0 0 10s Day of Day of Month Day of Month: 01-31 Month 0x1FFFC 0 0 0 0 0 Day of Week Day of week: 01-07 0x1FFFB 0 0 10s Hours Hours Hours: 00-23 0x1FFFA 0 10s Minutes Minutes Minutes: 00-59 0x1FFF9 0 10s Seconds Seconds Seconds: 00-59 0x1FFF8 OSCEN 0Cal Calibration[00000] Calibration values* [0] Sign 0x1FFF7 WDS WDW WDT
Summary of the content on the page No. 18
STK17TA8 Register Map Detail Real Time Clock – Years 0x1FFFF D7 D6 D5 D4 D3 D2 D1 D0 10s Years Years Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper nibble contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0-99. Real Time Clock – Months 0x1FFFE D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 10s Month Months Contains the BCD digits of the month. Lower nibble contains the lower digit and operates from 0 to 9; uppe
Summary of the content on the page No. 19
STK17TA8 Register Map Detail (continued) Watchdog Timer 0x1FFF7 D7 D6 D5 D4 D3 D2 D1 D0 WDS WDW WDT WDS Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. The bit is cleared automatically once the watchdog timer is reset. The WDS bit is write only. Reading it always will return a 0. WDW Watchdog Write Enable. Set this bit to 1 to disable writing of the watchdog time-out value (WDT5-WDT0). This allows the user to strobe the watchdog stobe bit without disturbing the
Summary of the content on the page No. 20
STK17TA8 Register Map Detail (continued) Alarm – Seconds 0x1FFF2 D7 D6 D5 D4 D3 D2 D1 D0 M 10s Alarm Seconds Alarm Seconds Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value. M Match. Setting this bit to 0 causes the seconds’ value to be used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the seconds value. 0x1FFF1 Real Time Clock – Centuries D7 D6 D5 D4 D3 D2 D1 D0 10s Centuries Centuries Contains the BCD value of ce
