Summary of the content on the page No. 1
21555 PCI-to-PCI Bridge
Evaluation Board
User’s Guide
November 2002
Order Number: 278359-002
Summary of the content on the page No. 2
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, m
Summary of the content on the page No. 3
Contents 1 Introduction.........................................................................................................................5 1.1 Overview ...............................................................................................................5 1.2 Features ................................................................................................................5 1.3 Major Components.................................................................................
Summary of the content on the page No. 4
Tables 1 DIP Switch Operation............................................................................................9 2 Stake-Pin Jumper .................................................................................................9 3 Clock Configuration Jumpers ..............................................................................11 4 Voltage Clamp.....................................................................................................11 5 Slot and IDSEL Mapping.....
Summary of the content on the page No. 5
Introduction 1 This User’s Guide describes the 21555 PCI-to-PCI nontransparent Bridge Evaluation Board which is referred to as the DE1B55503. 1.1 Overview The DE1B55503 is a PCI expansion board that is used to evaluate the operation of the 21555 when it is used as a gateway to an intelligent subsystem. The subsystem can use a variety of PCI devices and local processors. The DE1B55503 can be used to: Develop initialization code to configure the 21555 and associated logic and devices on the
Summary of the content on the page No. 6
Introduction 1.3 Major Components Figure 1 on page 6 shows the major components on the DE1B55503. Figure 1. Major Components PCI option and slot 2 SLOT 2 J7 1 E9 J101 J8 SLOT 1 E8 PCI option and PICMG slot OPTIONAL J102 E7 SLOT OPTIONAL SLOT Mictor Connectors for logic analyzers and Parallel E5 oscilloscopes ROM J4 J6 J2 Y1 E3 1 2 3 4 5 J21 J5 1 2 3 4 5 E2 E4 J1 J20 21555 1 2 3 4 5 J9 E1 JTAG Serial Initialization Clock Buffer Connector ROM Switches A8408-01 1.3.1 Connectors J1 is the 10-pin
Summary of the content on the page No. 7
Introduction Note: See Table A-2 on page 24 for Mictor pinouts. 1.3.2 Switches and Jumper The DE1B55503 uses a combination of DIP switch, stake-pin and zero ohm resistor jumpers to control the various configuration options. See Section 1.4, Section 1.5, and Section 1.6 for information. J8 is a single stake pin jumper. See Section 1.5 for information. J9, J20, and J21 are five-switch switch packs. The dual-pole switches are labeled SW1 through SW5. They control the options at power up such
Summary of the content on the page No. 8
Introduction 1.4 Switch Settings Figure 2 shows the three initialization switch packs, and Table 1 on page 9 gives a high-level description of each switch. The switches are read at DE1B55503 power up. Further details on the operation of these switches can be found in Chapter 3, “Optional Configurations”. The switches are in dual-in-line (DIP) packs designated J9, J20, and J21. Each switch pack contains SW1 through SW5. Figure 2. Switches SLOT 2 J7 E9 J101 J8 SLOT 1 E8 J102 E7 OPTIONAL SLOT I
Summary of the content on the page No. 9
Introduction Table 1. DIP Switch Operation Switch Switch The Switch Controls Reference Information Pack SW1, 2, 3 PICMG configurations. (See Chapter 3). Table 10 on page 21 J9 21555 Non Transparent SW4 PR_AD1 strapping option. PCI-to-PCI Bridge User’s Manual SW5 PR_CS to either Flash or optional ROM socket. Table 8 on page 19 SW1 PR_AD2 for SROM operation. J20 Table 7 on page 18 SW2 PR-AD3 for lockout bit control. SW3 PR_AD4 for synchronous or asynchronous clocking. Table 14 on page
Summary of the content on the page No. 10
Introduction 1.6 Resistor Jumpers Figure 3 shows the location of the zero (0) ohm resistor configuration jumpers. They control the clock configuration and the clamping voltage. To alter the factory configuration of the DE1B55503, the jumpers must be soldered on or off the DE1B55503 board. See Appendix A, “Signal and Default Information”. Figure 3. Jumper Resistors SLOT 2 J7 E9 J101 J8 R72 SLOT 1 E8 R69 J102 E7 OPTIONAL SLOT J4 J6 J2 E5 Y1 R93 1 2 3 4 5 E3 R100 J21 R73 J5 1 2 3 4 5 R66 E2 E4
Summary of the content on the page No. 11
Introduction 1.6.1 Clock Configuration Table 3 describes the resistor jumpers to install that connect p_clk and s_clk_o to the Mictor connectors. To improve signal integrity and minimize noise, these signals are not wired to the Mictor connectors. Resistor jumpers also control the selection of clock signals. See Figure 3 on page 10 for the resistor jumper locations. See Table A-3 on page 24 for Mictor pinouts. Table 3. Clock Configuration Jumpers Clock Source Installed Removed Use the s_clk_
Summary of the content on the page No. 12
Introduction 1.7 Secondary Slot Numbering and IDSEL Mapping Figure 4 gives the bus slot numbering. Table 5 shows how a Product Name numbers the Local slots in response to a Type 0 or Type 1 configuration cycle. The local bus lines s_ad<24> and s_ad<31:28> are used as local Initilization Device Select (IDSEL) lines. Figure 4. Local PCI Slot Numbering PCI option and slot Device 20/Zero (0) 2 SLOT 2 J7 E9 J101 J8 1 SLOT 1 PCI option and PICMG E8 slot - Device 13/13 OPTIONAL J102 SLOT E7 OPTI
Summary of the content on the page No. 13
Introduction 1.8 Interrupt Routing Table 6 shows the ORing of interrupts. 12 interrupts are connected to each of three secondary bus PCI slots but four (4) interrupts are driven to the card edge. The 12 incoming interrupts must be combined. Interrupt ORing is in accordance with the PCI-to-PCI Bridge Architecture Specification revision 1.1. Table 6. Interrupt ORing Interrupt Pin on Interrupt Pin on Board Device Number Device Connector INTA# INTB# 5 INTB# INTC# (Optional slot J101) INTC# INTD#
Summary of the content on the page No. 14
Introduction 1.9 Typical Configurations Figure 5 shows the DE1B55503 with one local bus option card. The option card can be either 32-bit or 64-bit. Figure 5. DE1B55503 with One Local Bus Option Card ADD-IN CARD J7 J8 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 21555 A8412-01 14 21555 PCI-to-PCI Bridge Evaluation Board User’s Guide L1+ L2
Summary of the content on the page No. 15
Introduction Figure 6 shows the DE1B55503 with two local bus option cards. Figure 6. DE1B55503 with Two Local Bus Option Cards ADD-IN CARD J7 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 21555 A8413-01 21555 PCI-to-PCI Bridge Evaluation Board User’s Guide 15 L1+ L2
Summary of the content on the page No. 16
Summary of the content on the page No. 17
Operations and Installation 2 This chapter provides DE1B55503 specifications and information about the hardware and software requirements for using the DE1B55503. It also describes how to install the DE1B55503. 2.1 Specifications This sections describes some overall specifications for the DE1B55503 board: Physical dimensions: Height: 15.2 cm (6.0 in) Width: 17.8 cm (7.0 in) Power requirements: DC amps @ 5 V: 2 A (maximum) On Board 3.3V regulator for S_VIO and Vdd 5A (Maximum) 2.2 Hardwa
Summary of the content on the page No. 18
Operations and Installation MSKROM.EXE an executable utility for programming the SROM. The software diskettes are standard 3.5 inch floppy disks. Follow the installation procedure printed on the inside of the shipping package. Be certain that the target system meets the minimum system requirements. 2.3.1 Programming the SROM To program the SROM on the DE1B55503, use the MKSROM.EXE utility. Use a text editor to create an ASCII data file. MSKSROM file.dat Where: MSKROM Executes the MSKROM
Summary of the content on the page No. 19
Operations and Installation 2.3.2.1 Board Setup Table 8 gives the DE1B55503 switch configuration for using the DBFLASH.EXE utility. Table 8. Switch Operation for FLASH programming Switch a Switch Switch Down Switch Up Description Pack Program and access Enables DBFLASH access to the ROM J9 SW5 ROM Socket pr_cs memory using Socket or to the flash memory. See DBFLASH.EXE. Figure 1 on page 6. a. Default configuration. 2.3.2.2 Running DbFlash.exe Make sure that both DBFLASH.EXE and DOS4GW.EXE are
Summary of the content on the page No. 20
Operations and Installation connectors and one (1) connector-less slot. Section 1.9, “Typical Configurations” on page 14 shows examples of typical PCI configurations. 6. Apply power to the system. 7. Verify the auto-configuration of the 21555 and other options. a. If the on-board ROM is preloaded the 21555 banner displays. b. Verify that system BIOS or firmware detects and configures the 21555. c. To verify the loading of the SROM, run the MKSROM utility without an SROM file as an input. See
