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User’s Guide
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OME-A8111 ISA-BUS
Multi-Functional Board
Hardware Manual
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OME-A-8111 Hardware User’s Manual OME-A-8111 Hardware Manual (ver.1.1, Jul/2003) 1
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Table of Contents 1. Introduction_________________________________________________________4 1.1 General Description ___________________________________________________ 4 1.2 Features _____________________________________________________________ 4 1.3 Specifications _________________________________________________________ 5 1.3.1 Power Consumption _________________________________________________________5 1.3.2 Analog Inputs___________________________________________________
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2.7.2 A/D Conversion Trigger Modes _______________________________________________ 22 2.7.3 A/D Transfer Modes________________________________________________________23 2.7.4 Using software trigger and polling transfer ______________________________________ 23 2.8 D/A Conversion ______________________________________________________ 24 2.9 Analog Input Signal Connection ________________________________________ 25 2.10 Pin Assignment ________________________________________________
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1. Introduction 1.1 General Description The OME-A-8111 is a high performance, multifunction (analog and digital I/O) board for the PC AT compatible computer with the ISA bus. The OME-A-8111 provides programmable gain (1, 2, 4, 8 and 16). The OME-A-8111 contains a 12-bit ADC with up to 8 single-ended analog inputs. The maximum sample rate of the A/D converter is about 30K sample/sec. There is a 12-bit DAC with voltage outputs, 16 channels of TTL-compatible digital input, and 16 cha
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1.3 Specifications 1.3.1 Power Consumption +5V @ 300 mA maximum +12V @ 60 mA maximum -12V @ 30 mA maximum Operating temperature: 0 °C ~ 50 °C 1.3.2 Analog Inputs Channels: 8 single-ended Input range: (software programmable) Bipolar: ±5 V, ±2.5 V, ±1.25 V, ±0.625 V, ±0.3125 V Input current: 250 nA max (125 nA typical) at 25 °C On-chip sample and hold Over voltage: continuous single channel to 70Vp-p 1.3.3 A/D Converter Type: successive approxim
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1.3.4 DA Converter Channels : 1 independent Type : 12-bit multiplying , Analog device AD-7948 Linearity : ± 1/2 bit Output Range : 0~5 V or 0~10 V jumper selected , may be used with other AC or DC reference input. Maximum output limit ± 10V Output Drive : ± 5 mA Settling Time : 0.6 microseconds to 0.01% for full scale step 1.3.5 Digital I/O Output port : 16 bits, TTL compatible Input port : 16 bits, TTL compatible 1.3.6 Interrupt Channel Le
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1.3.7 Programmable Timer/Counter Type : 82C54 -8 programmable timer/counter Counters: The counter1 and counter2 are cascaded as a 32-bit pacer timer. Pacer output : 0.00047 Hz to 0.5 MHz Input Gate : TTL compatible Internal Clock : 2 MHz 1.3.8 Applications Signal analysis FFT & frequency analysis Transient analysis Production test Process control Vibration analysis Energy management Industrial and laboratory measurement and control 1.4 Product Check
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BASS ADDRESS JP1 8111 () 987 654 A JP2 ON SW1 1234 56 VR1 VR2 VR3 VR4 VR5 12 ANA I/0 CN1 19 20 1 2 19 20 A1 P1 A31 2. Hardware Configuration 2.1 Board Layout CN2 D/C IN CN3 D/C OUT BB ADS-774 OME-A-8111 Hardware Manual (ver.1.1, Jul/2003) 8
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2.2 I/O Base Address Setting The OME-A-8111 occupies 16 consecutive locations in I/O address space. The base address is set by DIP switch SW1. The default address is 0x220 as shown below: A9 A8 A7 A6 A5 A4 ON 1 2 3 4 5 6 SW1 : BASE ADDRESS BASE ADDR A9 A8 A7 A6 A5 A4 200-20F OFF ON ON ON ON ON 210-21F OFF ON ON ON ON OFF 220-22F( ) OFF ON ON ON OFF ON 230-23F OFF ON ON ON OFF OFF : : : : : : : 300-30F OFF OFF ON ON ON ON :
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The PC I/O port mapping is given below. ADDRESS DEVICE ADDRESS DEVICE 000-1FF PC reserved 320-32F XT Hard Disk 200-20F Game/control 378-37F Parallel Printer 210-21F XT Expansion Unit 380-38F SDLC 238-23F Bus Mouse/Alt. Bus Mouse 3A0-3AF SDLC 278-27F Parallel Printer 3B0-3BF MDA/Parallel Printer 2B0-2DF EGA 3C0-3CF EGA 2E0-2E7 AT GPIB 3D0-3DF CGA 2E8-2EF Serial Port 3E8-3EF Serial Port 2F8-2FF Serial Port 3F0-3F7 Floppy Disk 300-31F Prototype Card 3F8-3FF Serial Port 2.3 Jum
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2.4 I/O Register Address The OME-A-8111 occupies 16 consecutive PC I/O addresses. The following table lists the registers and their locations. Address Read Write Base+0 8254 Counter 0 8254 Counter 0 Base+1 8254 Counter 1 8254 Counter 1 Base+2 8254 Counter 2 8254 Counter 2 Base+3 Reserved 8254 Counter Control Base+4 A/D Low Byte D/A Channel 0 Low Byte Base+5 A/D High Byte D/A Channel 0 High Byte Base+6 DI Low Byte Reserved Base+7 DI High Byte Reserved Base+8 Reserved A/D Clear I
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2.4.1 The 8254 Counter The 8254 Programmable timer/counter has 4 registers from Base+0 through Base+3. For detailed programming information about the 8254, please refer to Intel‘s “Microsystem Components Handbook”. Address Read Write Base+0 8254 Counter 0 8254 Counter 0 Base+1 8254 Counter 1 8254 Counter 1 Base+2 8254 Counter 2 8254 Counter 2 Base+3 Reserved 8254 Counter Control 2.4.2 A/D Input Buffer Register (READ) Base+4: A/D Low Byte Data Format Bit 7 Bit 6 Bit 5
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2.4.3 D/A Output Latch Register (WRITE) Base+4: Channel 1 D/A Low Byte Data Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D7 D6 D5 D4 D3 D2 D1 D0 (WRITE) Base+5: Channel 1 D/A High Byte Data Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X D11 D10 D9 D8 D/A 12 bit output data: D11…D0, D11 = MSB, D0 = LSB, X = don‘t care The D/A converter will convert the 12 bits of digital data to analog output. The low 8 bits of D/A channel are stored in address BASE
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2.4.5 Clear Interrupt Request (WRITE) Base+8: Clear Interrupt Request Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X X X X X X = don‘t care, XXXXXXXX = any 8 bit data is valid If OME-A-8111 is working in the interrupt transfer mode, an on-board hardware status bit will be set after each A/D conversion. This bit must be cleared by the software before next hardware interrupt. Writing any value to address BASE+8 will clear this hardware bit and the hardware will gener
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2.4.7 A/D Multiplex Control Register (WRITE) Base+A : A/D Multiplexer Control Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X X D2 D1 D0 A/D input channel selection data =3 bits: D2...D0, D2=MSB, D0=LSB, X=don‘t care Channel Bit_2 Bit_1 Bit_0 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 NOTE: The settling time of the multiplexer depends on the source resistance of input sources. Approx. Source resistance = 0.1
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2.4.8 A/D Mode Control Register (WRITE) Base+B : A/D Mode Control Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X SI2 SI1 SI0 X D2 D1 D0 X=don‘t care Mode Select Trigger Type Transfer Type D2 D1 D0 Software Trig Pacer Trig Software Interrupt 0 0 0 Select X Select X 0 0 1 Select X Select X 0 1 0 X Select X X 1 1 0 X Select Select Select X=disable SI2 SI1 SI0 IRQ Level 0 0 0 IRQ2 0 0 1 Not used 0 1 0 IRQ2 0 1 1 IRQ3 1 0 0 IRQ4 1 0 1 IRQ5 1 1 0 IRQ6 1
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The pacer trigger can control the sampling rate very precisely. So the converted data can be used to reconstruct the waveform of the analog input signal. In pacer trigger mode, the pacer timer will periodically generate trigger signals to the A/D converter. This converted data can be transfer to the CPU by polling or interrupt or DMA transfer method. The software driver provides three polling or interrupt-transfer methods. The polling subroutine, A8111_AD_PollingVar() or A822_AD_PollingA
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2.4.10 D/O Output Latch Register (WRITE) Base+D: D/O Output Latch Low Byte Data Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D7 D6 D5 D4 D3 D2 D1 D0 (WRITE) Base+E: D/O Output Latch High Byte Data Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D15 D14 D13 D12 D11 D10 D9 D8 D/O 16 bits output data: D15...D0, D15=MSB, D0=LSB The OME-A-8111 provides 16 TTL compatible digital outputs. The low 8 bits are stored in address BASE+D. The high 8 bits are stored in addre
