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uPSD3212A, uPSD3212C
uPSD3212CV
Flash Programmable System Devices with
8032 MCU with USB and Programmable Logic
FEATURES SUMMARY
■ FAST 8-BIT 8032 MCU Figure 1. Packages
– 40MHz at 5.0V, 24MHz at 3.3V
– Core, 12-clocks per instruction
■ DUAL FLASH MEMORIES WITH MEMORY
MANAGEMENT
– Place either memory into 8032 program
address space or data address space
TQFP52 (T)
– READ-while-WRITE operation for In-
52-lead, Thin,
Application Programming and EEPROM
Quad, Flat
emulation
– Single voltage prog
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uPSD3212A, uPSD3212C, uPSD3212CV Table 1. Device Summary Max 1st 2nd SRAM 8032 V CC Part Number Clock Flash Flash GPIO USB Pkg. Temp. (bytes) Bus (V) (MHz) (bytes) (bytes) uPSD3212C-40T6 40 64K 16K 2K 37 No No 4.5-5.5 TQFP52 –40°C to 85°C uPSD3212CV-24T6 24 64K 16K 2K 37 No No 3.0-3.6 TQFP52 –40°C to 85°C uPSD3212C-40U6 40 64K 16K 2K 46 No Yes 4.5-5.5 TQFP80 –40°C to 85°C uPSD3212CV-24U6 24 64K 16K 2K 46 No Yes 3.0-3.6 TQFP80 –40°C to 85°C uPSD3212A-40T6 40 64K 16K 2K 37 Yes No 4.5-5.5 TQFP52 –
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uPSD3212A, uPSD3212C, uPSD3212CV TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 52-PIN PACKAGE I/O PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ARCHITECTURE OVERVIEW . . . .
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uPSD3212A, uPSD3212C, uPSD3212CV Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 I/O PORTS (MCU Module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 PORT Type and Description. . . . . .
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uPSD3212A, uPSD3212C, uPSD3212CV In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET . . . . . . . . . . . . . . . . . . . . . . . . 92 PSD MODULE DETAILED OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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uPSD3212A, uPSD3212C, uPSD3212CV PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 RESET TIMING AND DEVICE STATUS AT RESET . . . .
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uPSD3212A, uPSD3212C, uPSD3212CV SUMMARY DESCRIPTION The uPSD321x Series combines a fast 8051- Dual Flash memory banks provide a robust solu- based microcontroller with a flexible memory tion for remote product updates in the field through structure, programmable logic, and a rich periph- In-Application Programming (IAP). Dual Flash eral mix including USB, to form an ideal embedded banks also support EEPROM emulation, eliminat- controller. At its core is an industry-standard 8032 ing the need fo
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 3. TQFP52 Connections PD1/CLKIN 1 39 P1.5/ADC1 PC7 2 38 P1.4/ADC0 JTAG TDO 3 37 P1.3/TXD1 JTAG TDI 4 36 P1.2/RXD1 (1) USB– 5 35 P1.1/T2X PC4/TERR_ 6 34 P1.0/T2 USB+ 7 33 V CC V 8 32 XTAL2 CC GND 9 31 XTAL1 PC3/TSTAT 10 30 P3.7/SCL1 PC2/V 11 29 P3.6/SDA1 STBY JTAG TCK 12 28 P3.5/T1 JTAG TMS 13 27 P3.4/T0 AI07423c Note: 1. Pull-up resistor required on pin 5 (2kΩ for 3V devices, 7.5kΩ for 5V devices). 8/163 PB0 P4.7/PWM4 14 52 P4.6/PWM3 15 51 PB
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 4. TQFP80 Connections PD2 1 60 P1.5/ADC1 P3.3 /EXINT1 2 59 P1.4/ADC0 PD1/CLKIN 3 58 P1.3/TXD1 ALE 4 57 A11 PC7 5 56 P1.2/RXD1 JTAG/TDO 6 55 A10 JTAG/TDI 7 54 P1.1/TX2 (1) USB– 8 53 A9 PC4/TERR_ 9 52 P1.0/T2 USB+ 10 51 A8 (2) NC 11 50 V CC V 12 49 XTAL2 CC GND 13 48 XTAL1 PC3/TSTAT 14 47 AD7 PC2/V 15 46 P3.7/SCL1 STBY JTAG TCK 16 45 AD6 (2) NC 17 44 P3.6/SDA1 P4.7/PWM4 18 43 AD5 P4.6/PWM3 19 42 P3.5/T1 JTAG TMS 20 41 AD4 AI07424c Note:
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uPSD3212A, uPSD3212C, uPSD3212CV Table 2. 80-Pin Package Pin Description Function Signal Port Pin Pin No. In/Out Name Basic Alternate External Bus AD0 36 I/O Multiplexed Address/Data bus A1/D1 AD1 37 I/O Multiplexed Address/Data bus A0/D0 AD2 38 I/O Multiplexed Address/Data bus A2/D2 AD3 39 I/O Multiplexed Address/Data bus A3/D3 AD4 41 I/O Multiplexed Address/Data bus A4/D4 AD5 43 I/O Multiplexed Address/Data bus A5/D5 AD6 45 I/O Multiplexed Address/Data bus A6/D6 AD7 47 I/O Multiplexed Address/
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uPSD3212A, uPSD3212C, uPSD3212CV Function Signal Port Pin Pin No. In/Out Name Basic Alternate 8-bit Pulse Width Modulation P4.4 PWM1 25 I/O General I/O port pin output 1 8-bit Pulse Width Modulation P4.5 PWM2 23 I/O General I/O port pin output 2 8-bit Pulse Width Modulation P4.6 PWM3 19 I/O General I/O port pin output 3 Programmable 8-bit Pulse Width P4.7 PWM4 18 I/O General I/O port pin modulation output 4 Pull-up resistor required (2kΩ for 3V USB– 8 I/O devices, 7.5kΩ for 5V devices) V 70
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uPSD3212A, uPSD3212C, uPSD3212CV Function Signal Port Pin Pin No. In/Out Name Basic Alternate JTAG TMS 20 I JTAG pin JTAG TCK 16 I JTAG pin 1. PLD Macro-cell outputs V PC2 STBY 15 I/O General I/O port pin 2. PLD inputs 3. SRAM stand by voltage in- PC3 TSTAT 14 I/O General I/O port pin put (V ) STBY 4. SRAM battery-on indicator PC4 TERR_ 9 I/O General I/O port pin (PC4) 5. JTAG pins are dedicated JTAG TDI 7 I JTAG pin pins JTAG TDO 6 O JTAG pin PC7 5 I/O General I/O port pin 1. PLD I/O PD1 CLKIN
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uPSD3212A, uPSD3212C, uPSD3212CV ARCHITECTURE OVERVIEW Memory Organization The uPSD321x Devices’s standard 8032 Core has space. Refer to the PSD Module for details on separate 64KB address spaces for Program mem- mapping of the Flash memory. ory and Data Memory. Program memory is where The 8032 core has two types of data memory (in- the 8032 executes instructions from. Data memory ternal and external) that can be read and written. is used to hold data variables. Flash memory can The internal SRA
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uPSD3212A, uPSD3212C, uPSD3212CV Registers The 8032 has several registers; these are the Pro- [Parity Flag, P]. This flag reflects on number of Ac- gram Counter (PC), Accumulator (A), B Register cumulator’s “1.” If the number of Accumulator’s 1 (B), the Stack Pointer (SP), the Program Status is odd, P=0. otherwise, P=1. The sum of adding Word (PSW), General purpose registers (R0 to Accumulator’s 1 to P is always even. R7), and DPTR (Data Pointer register). R0~R7. General purpose 8-bit registers
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uPSD3212A, uPSD3212C, uPSD3212CV Figure 9. PSW (Program Status Word) Register MSB LSB CY AC FO RS1 RS0 OV P Reset Value 00h PSW Carry Flag Parity Flag Auxillary Carry Flag Bit not assigned General Purpose Flag Overflow Flag Register Bank Select Flags (to select Bank0-3) AI06639 Program Memory RAM The program memory consists of two Flash mem- Four register banks, each 8 registers wide, occupy ory: 64KByte Main Flash and 16KByte of Second- locations 0 through 31 in the lower RAM area. ary Flash. T
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uPSD3212A, uPSD3212C, uPSD3212CV SFR Addressing Modes The SFRs can only be addressed directly in the The addressing modes in uPSD321x Devices in- address range from 80h to FFh. Table struction set are as follows 15., page 28 gives an overview of the Special ■ Direct addressing Function Registers. Sixteen address in the SFRs ■ Indirect addressing space are both-byte and bit-addressable. The bit- ■ Register addressing addressable SFRs are those whose address ends in 0h and 8h. The bit addresses in
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uPSD3212A, uPSD3212C, uPSD3212CV (3) Register addressing. The register banks, Arithmetic Instructions containing registers R0 through R7, can be ac- The arithmetic instructions is listed in Table cessed by certain instructions which carry a 3-bit 4., page 18. The table indicates the addressing register specification within the opcode of the in- modes that can be used with each instruction to struction. Instructions that access the registers access the operand. For example, the this way ar
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uPSD3212A, uPSD3212C, uPSD3212CV Table 4. Arithmetic Instructions Addressing Modes Mnemonic Operation Dir. Ind. Reg. Imm ADD A, A = A + X X X X ADDC A, A = A + + C X X X X SUBB A, A = A – – C X X X X INC A = A + 1 Accumulator only INC = + 1 X X X INC DPTR DPTR = DPTR + 1 Data Pointer only DEC A = A – 1 Accumulator only DEC = – 1 X X X MUL AB B:A = B x A Accumulator and B only A = Int[ A / B ] DIV AB Accumulator and
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uPSD3212A, uPSD3212C, uPSD3212CV Table 5. Logical Instructions Addressing Modes Mnemonic Operation Dir. Ind. Reg. Imm ANL A, A = A .AND. X X X X ANL ,A A = .AND. A X ANL ,#data A = .AND. #data X ORL A, A = A .OR. X X X X ORL ,A A = .OR. A X ORL ,#data A = .OR. #data X XRL A, A = A .XOR. X X X X XRL ,A A = .XOR. A X XRL ,#data A = .XOR. #data X CRL A A = 00h Accumulator only CPL A
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uPSD3212A, uPSD3212C, uPSD3212CV Data Transfers Internal RAM. Table 6 shows the menu of in- The XCH A, instruction causes the Accu- structions that are available for moving data mulator and ad-dressed byte to exchange data. around within the internal memory spaces, and the The XCHD A, @Ri instruction is similar, but only addressing modes that can be used with each the low nibbles are involved in the exchange. To one. The MOV , instruction allows see how XCH and XCHD can be use
