Summary of the content on the page No. 1
110 MSPS/140 MSPS Analog Interface for
a
Flat Panel Displays
AD9883A
FEATURES FUNCTIONAL BLOCK DIAGRAM
140 MSPS Maximum Conversion Rate
300 MHz Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
8
R
CLAMP A/D R
AIN OUTA
500 ps p-p PLL Clock Jitter at 110 MSPS
3.3 V Power Supply
8
Full Sync Processing
G
CLAMP A/D
AIN G
OUTA
Sync Detect for ”Hot Plugging”
Midscale Clamping
8
Power-Down Mode B CLAMP A/D B
AIN OUTA
Low Power: 500 mW Typical
MIDSCV
4:2:2 Output Format Mode
HSYNC
DTACK
SYNC
APPLICATIO
Summary of the content on the page No. 2
AD9883A–SPECIFICATIONS Analog Interface (V = 3.3 V, V = 3.3 V, ADC Clock = Maximum Conversion Rate unless otherwise noted.) D DD Test AD9883AKST-110 AD9883AKST-140 Parameter Temp Level Min Typ Max Min Typ Max Unit RESOLUTION 8 8 Bits DC ACCURACY Differential Nonlinearity 25°CI ±0.5 +1.25/–1.0 ±0.5 +1.35/–1.0 LSB Full VI +1.35/–1.0 +1.45/–1.0 LSB Integral Nonlinearity 25°CI ±0.5 ±1.85 ±0.5 ±2.0 LSB Full VI ±2.0 ±2.3 LSB No Missing Codes Full VI Guaranteed Guaranteed ANALOG INPUT Input Voltage Ran
Summary of the content on the page No. 3
AD9883A Test AD9883AKST-110 AD9883AKST-140 Parameter Temp Level Min Typ Max Min Typ Max Unit DIGITAL OUTPUTS Output Voltage, High (V ) Full VI V – 0.1 V – 0.1 V OH D D Output Voltage, Low (V ) Full VI 0.1 0.1 V OL Duty Cycle DATACK Full IV 45 50 55 45 50 55 % Output Coding Binary Binary POWER SUPPLY V Supply Voltage Full IV 3.0 3.3 3.6 3.15 3.3 3.6 V D V Supply Voltage Full IV 2.2 3.3 3.6 2.2 3.3 3.6 V DD P Supply Voltage Full IV 3.0 3.3 3.6 3.0 3.3 3.6 V VD I Supply Current (V)25°C V 132 180 mA
Summary of the content on the page No. 4
AD9883A ABSOLUTE MAXIMUM RATINGS* EXPLANATION OF TEST LEVELS V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V Test Level D V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V I. 100% production tested. DD Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . V to 0.0 V D II. 100% production tested at 25°C and sample tested at VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V to 0.
Summary of the content on the page No. 5
AD9883A PIN CONFIGURATION 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 GND 60 GND PIN 1 GREEN <7> 2 IDENTIFIER 59 V D GREEN <6> 3 58 REF BYPASS 4 GREEN <5> 57 SDA 5 GREEN <4> 56 SCL GREEN <3> 6 55 A0 GREEN <2> 7 54 R AIN 8 GREEN <1> 53 GND 9 GREEN <0> 52 V D AD9883A GND 10 51 V TOP VIEW D 11 (Not to Scale) V 50 GND DD 12 BLUE <7> 49 SOGIN 13 BLUE <6> 48 G AIN 14 BLUE <5> 47 GND BLUE <4> 15 46 V D BLUE <3> 16 45 V D 17 BLUE <2> 44 GND 18 BLUE <1> 43 B AIN 19 BLUE <0> 42 V D GND 2
Summary of the content on the page No. 6
AD9883A PIN FUNCTION DESCRIPTIONS Pin Name Function OUTPUTS HSOUT Horizontal Sync Output A reconstructed and phase-aligned version of the Hsync input. Both the polarity and duration of this output can be programmed via serial bus registers. By maintaining alignment with DATACK, and Data, data timing with respect to horizontal sync can always be determined. VSOUT Vertical Sync Output A reconstructed and phase-aligned version of the video Vsync. The polarity of this output can be controlled via a
Summary of the content on the page No. 7
AD9883A PIN FUNCTION DESCRIPTIONS (continued) Pin Name Function CLAMP External Clamp Input This logic input may be used to define the time during which the input signal is clamped to ground. It should be exercised when the reference dc level is known to be present on the analog input channels, typically during the back porch of the graphics signal. The CLAMP pin is enabled by setting control bit Clamp Function to 1, (register 0FH, Bit 7, default is 0). When disabled, this pin is ignored and the
Summary of the content on the page No. 8
AD9883A producing a black output (code 00h) when the known black At that point the signal should be resistively terminated (75 Ω input is present. The offset then remains in place when other to the signal ground return) and capacitively coupled to the signal levels are processed, and the entire signal is shifted to elimi- AD9883A inputs through 47 nF capacitors. These capacitors nate offset errors. form part of the dc restoration circuit. In most PC graphics systems, black is transmitted between
Summary of the content on the page No. 9
AD9883A Clock Generation OFFSET = 7Fh A Phase Locked Loop (PLL) is employed to generate the pixel clock. In this PLL, the Hsync input provides a reference fre- OFFSET = 3Fh 1.0 quency. A Voltage Controlled Oscillator (VCO) generates a much higher pixel clock frequency. This pixel clock is divided OFFSET = 00h by the PLL divide value (registers 01H and 02H) and phase compared with the Hsync input. Any error is used to shift the 0.5 VCO frequency and maintain lock between the two signals. OFFSET =
Summary of the content on the page No. 10
AD9883A The PLL characteristics are determined by the loop filter design, 4. The 5-Bit Phase Adjust Register. The phase of the generated by the PLL Charge Pump Current and by the VCO range setting. sampling clock may be shifted to locate an optimum sampling The loop filter design is illustrated in Figure 6. Recommended point within a clock cycle. The Phase Adjust register provides settings of VCO range and charge pump current for VESA 32 phase-shift steps of 11.25° each. The Hsync signal with st
Summary of the content on the page No. 11
AD9883A Table V. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats Refresh Horizontal Standard Resolution Rate Frequency Pixel Rate VCORNGE Current VGA 640 × 480 60 Hz 31.5 kHz 25.175 MHz 00 101 72 Hz 37.7 kHz 31.500 MHz 00 110 75 Hz 37.5 kHz 31.500 MHz 00 110 85 Hz 43.3 kHz 36.000 MHz 00 110 SVGA 800 × 600 56 Hz 35.1 kHz 36.000 MHz 00 110 60 Hz 37.9 kHz 40.000 MHz 01 100 72 Hz 48.1 kHz 50.000 MHz 01 100 75 Hz 46.9 kHz 49.500 MHz 01 100 85 Hz 53.7 kHz 56.250 MHz
Summary of the content on the page No. 12
AD9883A RGB P0 P1 P2 P3 P4 P5 P6 P7 IN HSYNC PxCK HS 5-PIPE DELAY ADCCK DATACK D D0 D1 D2 D3 D4 D5 D6 D7 OUTA HSOUT VARIABLE DURATION Figure 8. 4:4:4 Mode (For RGB and YUV) RGB P0 P1 P2 P3 P4 P5 P6 P7 IN HSYNC PxCK HS 5-PIPE DELAY ADCCK DATACK G Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 OUTA R U0 V1 U2 V3 U4 V5 U6 V7 OUTA HSOUT Figure 9. 4:2:2 Mode (For YUV Only) –12– REV. 0
Summary of the content on the page No. 13
AD9883A 2-Wire Serial Register Map The AD9883A is initialized and controlled by a set of registers, which determine the operating modes. An external controller is employed to write and read the Control Registers through the 2-line serial interface port. Table VI. Control Register Map Write and Hex Read or Default Register Address Read Only Bits Value Name Function 00H RO 7:0 Chip Revision An 8-bit register that represents the silicon revision level. Revision 0 = 0000 0000 01H R/W 7:0 01101001 PL
Summary of the content on the page No. 14
AD9883A Table VI. Control Register Map (continued) Write and Hex Read or Default Register Address Read Only Bits Value Name Function 0FH R/W 7:1 0******* Bit 7 – Clamp Function. Chooses between HSYNC for Clamp signal or another external signal to be used for clamping. (Logic 0 = HSYNC, Logic 1 = Clamp.) *1****** Bit 6 – Clamp Polarity. Valid only with external Clamp signal. (Logic 0 = active high, Logic 1 select active low.) **0***** Bit 5 – Coast Select. Logic 0 selects the coast input pins to
Summary of the content on the page No. 15
AD9883A Table VI. Control Register Map (continued) Write and Hex Read or Default Register Address Read Only Bits Value Name Function 15H R/W 7:0 Test Register Bits [7:2] Reserved for future use. Bit 1 – 4:2:2 Output Formatting Mode. Bit 0 – Must be set to 0 for proper operation. 16H R/W 7:0 Test Register Reserved for future use. 17H RO 7:0 Test Register Reserved for future use. 18H RO 7:0 Test Register Reserved for future use. NOTE 1 The AD9883A only updates the PLL divide ratio when the LSBs ar
Summary of the content on the page No. 16
AD9883A 04 7–3 Clock Phase Adjust INPUT OFFSET A 5-bit value that adjusts the sampling phase in 32 steps 0B 7–1 Red Channel Offset Adjust across one pixel time. Each step represents an 11.25° shift A 7-bit offset binary word that sets the dc offset of the RED in sampling phase. channel. One LSB of offset adjustment equals approximately one LSB change in the ADC offset. Therefore, the absolute The power-up default value is 16. magnitude of the offset adjustment scales as the gain of the channel i
Summary of the content on the page No. 17
AD9883A 0E 5 Hsync Output Polarity 0E 0 Active Vsync Select One bit that determines the polarity of the Hsync output This bit is used to select the active Vsync when the over- and the SOG output. Table XI shows the effect of this ride bit is set (Bit 1). option. SYNC indicates the logic state of the sync pulse. Table XVI. Active Vsync Select Settings Table XI. Hsync Output Polarity Settings Select Result Setting SYNC 0 Vsync Input 0 Logic 1 (Positive Polarity) 1 Sync Separator Output 1 Logic 0 (
Summary of the content on the page No. 18
AD9883A 0F 4 Coast Input Polarity Override steps of 10 mV, with the minimum setting equaling 10 mV This register is used to override the internal circuitry that (11111) and the maximum setting equaling 330 mV (00000). determines the polarity of the coast signal going into The default setting is 23 and corresponds to a threshold the PLL. value of 0.15 V. 10 2 Red Clamp Select Table XX. Coast Input Polarity Override Settings A bit that determines whether the RED channel is clamped Override Bit Res
Summary of the content on the page No. 19
AD9883A 13 7-0 Post-Coast Table XXX. Vsync Detection Results This register allows the coast signal to be applied follow- Detect Function ing to the Vsync signal. This is necessary in cases where post-equalization pulses are present. The step size for this 0 No Activity Detected control is one Hsync period. 1 Activity Detected The default is 0. The Sync Processing Block Diagram (Figure 12) shows 14 7 Hsync Detect where this function is implemented. This bit is used to indicate when activity is de
Summary of the content on the page No. 20
AD9883A Table XXXIV. Detected Coast Input Polarity Status There are five components to serial bus operation: • Start Signal Hsync Polarity Status Result • Slave Address Byte 0 Coast Polarity Negative • Base Register Address Byte 1 Coast Polarity Positive • Data Byte to Read or Write • Stop Signal 15 7 4:2:2 Output Mode Select When the serial interface is inactive (SCL and SDA are high) A bit that configures the output data in 4:2:2 mode. communications are initiated by sending a start signal. Th
