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CC2420
2.4 GHz IEEE 802.15.4 / ZigBee-ready RF Transceiver
Applications
• 2.4 GHz IEEE 802.15.4 systems • Wireless sensor networks
• ZigBee systems • PC peripherals
• Home/building automation • Consumer Electronics
• Industrial Control
Product Description
features reduce the load on the host
The CC2420 is a true single-chip 2.4 GHz
IEEE 802.15.4 compliant RF transceiver controller and allow CC2420 to interface
designed for low power and
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CC2420 Table of contents 1 Abbreviations_________________________________________________________________5 2 References ___________________________________________________________________6 3 Features _____________________________________________________________________7 4 Absolute Maximum Ratings _____________________________________________________8 5 Operating Conditions __________________________________________________________8 6 Electrica
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CC2420 17 RF Data Buffering __________________________________________________________39 17.1 Buffered transmit mode_____________________________________________________39 17.2 Buffered receive mode _____________________________________________________39 17.3 Unbuffered, serial mode ____________________________________________________40 18 Address Recognition ________________________________________________________41 19 Acknowledge Frames _____
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CC2420 40.1 Package thermal properties __________________________________________________84 40.2 Soldering information ______________________________________________________84 40.3 Plastic tube specification ____________________________________________________85 40.4 Carrier tape and reel specification _____________________________________________85 41 Ordering Information _______________________________________________________85 42 General Inf
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CC2420 1 Abbreviations ADC - Analog to Digital Converter AES - Advanced Encryption Standard AGC - Automatic Gain Control ARIB - Association of Radio Industries and Businesses BER - Bit Error Rate CBC-MAC - Cipher Block Chaining Message Authentication Code CCA - Clear Channel Assessment CCM - Counter mode + CBC-MAC CFR - Code of Federal Regulations CSMA-CA - Carrier Sense Multiple Access with Collision Avoidance CTR - Counter mode
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CC2420 SHR - Synchronisation Header SPI - Serial Peripheral Interface TBD - To Be Decided / To Be Defined T/R - Transmit / Receive TX - Transmit VCO - Voltage Controlled Oscillator VGA - Variable Gain Amplifier 2 References [1] IEEE std. 802.15.4 - 2003: Wireless Medium Access Control (MAC) and Physical Layer (PHY) specifications for Low Rate Wireless Personal Area Networks (LR-WPANs) http://standards.ieee.org/getieee802/download/
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CC2420 3 Features • 2400 – 2483.5 MHz RF Transceiver • 802.15.4 MAC hardware support: • Direct Sequence Spread • Automatic preamble generator Spectrum (DSSS) transceiver • Synchronisation word • 250 kbps data rate, 2 MChip/s insertion/detection chip rate • CRC-16 computation and • O-QPSK with half sine pulse checking over the MAC payload shaping modulation • Clear Channel Assessment • Very low current consumption • Energy detection / digi
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CC2420 4 Absolute Maximum Ratings Parameter Min. Max. Units Condition Supply voltage for on-chip voltage regulator, -0.3 3.6 V VREG_IN pin 43. Supply voltage (VDDIO) for digital I/Os, DVDD3.3, -0.3 3.6 V pin 25. Supply voltage (VDD) on AVDD_VCO, DVDD1.8, −0.3 2.0 V etc (pin no 1, 2, 3, 4, 10, 14, 15, 17, 18, 20, 26, 35, 37, 44 and 48) Voltage on any digital I/O pin, (pin no. 21, 27-34 -0.3 VDDIO+0.3, max 3.6 V and 41) Voltage on any o
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CC2420 6 Electrical Specifications Measured on CC2420 EM with transmission line balun, T = 25 °C, DVDD3.3 and VREG_IN = 3.3 V, internal A voltage regulator used if nothing else stated. 6.1 Overall Parameter Min. Typ. Max. Unit Condition / Note RF Frequency Range 2400 2483.5 MHz Programmable in 1 MHz steps, 5 MHz steps for compliance with [1] 6.2 Transmit Section Parameter Min. Typ. Max. Unit Condition / Note Transmit bit rate 250 250 k
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CC2420 6.3 Receive Section Parameter Min. Typ. Max. Unit Condition / Note Receiver Sensitivity -90 -95 dBm PER = 1%, as specified by [1] Measured in a 50Ω single-ended load through a balun. [1] requires –85 dBm Saturation (maximum input level) 0 10 dBm PER = 1%, as specified by [1] Measured in a 50Ω single–ended load through a balun. [1] requires –20 dBm Adjacent channel rejection Wanted signal @ -82 dBm, adjacent modulated
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CC2420 Parameter Min. Typ. Max. Unit Condition / Note Frequency error tolerance -300 300 kHz Difference between centre frequency of the received RF signal and local oscillator frequency [1] requires 200 kHz Symbol rate error tolerance 120 ppm Difference between incoming symbol rate and the internally generated symbol rate [1] requires 80 ppm Data latency 3 µs Processing delay in receiver. Time from complete transmission of SFD until
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CC2420 Parameter Min. Typ. Max. Unit Condition / Note Crystal load capacitance 12 16 20 pF 16 pF recommended Crystal ESR 60 Ω Crystal oscillator start-up time 1.0 ms 16 pF load Phase noise Unmodulated carrier −109 dBc/Hz At ±1 MHz offset from carrier −117 dBc/Hz At ±2 MHz offset from carrier −117 dBc/Hz At ±3 MHz offset from carrier −117 dBc/Hz At ±5 MHz offset from carrier PLL loop bandwidth 100 kHz PLL lock time
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CC2420 6.8 Voltage Regulator Parameter Min. Typ. Max. Unit Condition / Note General Note that the internal voltage regulator can only supply CC2420 and no external circuitry. Input Voltage 2.1 3.0 3.6 V On the VREG_IN pin Output Voltage 1.7 1.8 1.9 V On the VREG_OUT pin Quiescent current 13 20 29 No current drawn from the µA VREG_OUT pin. Min and max numbers include 2.1 through 3.6 V input voltage Start-up time 0.3 0.6 ms
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CC2420 Parameter Min. Typ. Max. Unit Condition / Note Current Consumption, transmit mode: P = -25 dBm 8.5 mA The output power is delivered P = -15 dBm 9.9 mA differentially to a 50 Ω singled P = -10 dBm 11 mA ended load through a balun, see P = −5 dBm 14 mA also page 54. P = 0 dBm 17.4 mA SWRS041B Page 14 of 89
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24 DSUB_CORE DSUB_PADS 23 22 DGND RESETn 21 DGUARD 20 DGND_GUARD 19 18 DVDD_ADC 17 AVDD_ADC 16 NC AVDD_IF2 15 14 AVDD_RF2 NC 13 CC2420 7 Pin Assignment VCO_GUARD 1 36 NC AVDD_VCO 2 35 DVDD_RAM AVDD_PRE 3 34 SO 4 33 SI AVDD_RF1 32 SCLK GND 5 RF_P 6 QLP48 31 CSn 7x7 CC2420 7 30 FIFO TXRX_SWITCH 8 29 FIFOP RF_N GND 9 28 CCA AVDD_SW 10 27 SFD NC 11 26 DVDD1.8 12 25 NC DVDD3.3 AGND Exposed die attach pad Figure 1. CC2420 Pinout – Top View Pin Pi
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CC2420 Pin Pin Name Pin type Pin Description NC 16 - Not Connected AVDD_ADC 17 Power (analog) 1.8 V Power supply for analog parts of ADCs and DACs DVDD_ADC 18 Power (digital) 1.8 V Power supply for digital parts of receive ADCs DGND_GUARD 19 Ground (digital) Ground connection for digital noise isolation DGUARD 20 Power (digital) 1.8 V Power supply connection for digital noise isolation RESETn 21 Digital Input Asynchronous, active low dig
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CC2420 8 Circuit Description AUTOMATIC GAIN CONTROL DIGITAL ADC DEMODULATOR - Digital RSSI Serial - Gain Control LNA voltage - Image Suppression - Channel Filtering regulator - Demodulation - Frame ADC synchronization TX/RX CONTROL DIGITAL ® INTERFACE SmartRF 0 FREQ WITH FIFO SYNTH BUFFERS, 90 CRC AND CC2420 ENCRYPTION TX POWER CONTROL DAC DIGITAL Power MODULATOR Control Digital and - Data spreading PA Σ Analog test - Modulation interface
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CC2420 and Q LO signals to the down-conversion The 4-wire SPI serial interface is used for mixers in receive mode and up-conversion configuration and data buffering. mixers in transmit mode. The VCO operates in the frequency range 4800 – An on-chip voltage regulator delivers the 4966 MHz, and the frequency is divided by regulated 1.8 V supply voltage. The two when split in I and Q. voltage regulator may be enabled / disabled through a separa
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CC2420 9 Application Circuit Few external components are required for If a balanced antenna such as a folded the operation of CC2420. A typical dipole is used, the balun can be omitted. If the antenna also provides a DC path from application circuit is shown in Figure 4. The external components shown are the TXRX_SWITCH pin to the RF pins, described in Table 1 and typical values inductors are not needed for DC bias. are given in Table 2. Note
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DSUB_CORE 24 DSUB_PADS 23 22 DGND RESETn 21 DGUARD 20 DGND_GUARD 19 18 DVDD_ADC AVDD_ADC 17 NC 16 AVDD_IF2 15 AVDD_RF2 14 NC 13 CC2420 Ref Description C42 Voltage regulator load capacitance C61 Balun and match C62 DC block to antenna and match C71 Front-end bias decoupling and match C81 Balun and match C381 16MHz crystal load capacitor, see page 53 C391 16MHz crystal load capacitor, see page 53 L61 DC bias and match L62 DC bias and match L
