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Intel® Atom™ Processor and
Intel® System Controller Hub
US15W Development Kit
User’s Manual
July 2008
Document #: 320264
Revision 1.0
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING T
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Contents 1 Introduction.....................................................................................................7 1.1 About the Development Kit......................................................................7 1.2 Terminology ..........................................................................................8 1.3 Technical Support...................................................................................9 1.3.1 Additional Technical Support........
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4.5 Manual VID Support for CPU ..................................................................32 4.6 Power On and Reset Push Buttons ..........................................................33 4.7 LEDs ..................................................................................................34 4.8 PCI Express* X1 Slots and Mini Card Connectors.......................................35 4.8.1 Mini Card A connector (J7H1) is enabled by default ......................35 4.
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Figures Figure 1. Crown Beach Board Block Diagram.......................................................11 Figure 2. Crown Beach Board (Top View)............................................................12 Figure 3. Crown Beach Board Feature Placement .................................................27 Figure 4. Back Panel Connectors .......................................................................28 Figure 5. Location of the Configuration Jumpers/Switches...............
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Revision History Document Revision Description Number Number 394649 1.0 Initial release. 320264 1.0 Release for public posting § User’s Manual 6 Document Number: 320264
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Introduction 1 Introduction This manual describes the typical hardware set-up procedures, features, and use of the evaluation board and other components included in the Intel® Atom™ processor and Intel® System Controller Hub US15W Development Kit. This reference board supports the Intel® Atom™ processor and Intel® System Controller Hub (Intel® SCH). Note: Read this document in its entirety prior to applying power to the motherboard. Intel recommends having both the schematic a
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Introduction Note: Not all peripherals listed will be included with a Crown Beach board. 1.2 Terminology Term Definition ACPI Advanced Configuration Power Interface ADD2 Advanced Digital display 2 card ADD2R Advanced Digital display 2 card with PCI-E graphics lane reversed (not supported on Crown Beach) CRB Customer Reference Board BGA Ball Grid Array DDR Double Data Rate DMA Direct Memory Access Duck Bay 3 PCI Express* interposer card that provides ExpressCard* sup
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Introduction Term Definition OS Operating System PATA Parallel AT Attachment PC Personal Computer PCB Printed Circuit Board PCIe* PCI Express* PEG PCI Express* Graphics PLL Phase Lock Loop PGA Pin Grid Array RTC Real Time Clock SCH System Controller Hub SD Secure Digital SDVO Serial Digital Video Output SIO Super Input Output SMC System Management Controller SO-DIMM Small Outline Dual In-line Memory Module TPM Trusted Platform Module TSSOP Thin Shrink Sma
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Introduction 1.4 Product Literature You can order product literature from the following Intel literature centers. Table 1. Intel Literature Centers U.S and Canada 1-800-548-4725 U.S. (from overseas) 708-296-9333 Europe (U.K.) 44(0)1793-431155 Germany 44(0)1793-421333 France 44(0)1793-421777 Japan (fax only) 81(0)120-47-88-32 1.5 Related Documents Table 2 is a partial list of the available collateral. For the complete list, contact your local Intel representative. Table 2.
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Crown Beach Board 2 Crown Beach Board Figure 1. Crown Beach Board Block Diagram User’s Manual 11 Document Number: 320264
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Crown Beach Board Figure 2. Crown Beach Board (Top View) 2.1 Getting Started This section identifies the key components, features and specifications of the Intel® Atom™ processor with Intel® System Controller Hub US15W Development Kit. It also describes how to set up the board for operation. Development software is included in the kit. User’s Manual 12 Document Number: 320264
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Crown Beach Board Note: This manual assumes a familiarity with basic concepts involved with installing and configuring hardware for a PC. 2.2 Overview The development kit contains a baseboard with an Intel® Atom™ processor Z530, Intel® System Controller Hub US15W, other system board components and peripheral connectors. Note: The evaluation board is shipped in a closed chassis. The user is required to observe extra precautions if the user opens the chassis for any reason. Note
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Crown Beach Board Feature Crown Beach Board Comments Implementation Single 24-bit LVDS interface; Through a 50-pin cable-up connector LVDS options Back Light Inverter (BLI) and (separate cables required for each LED backlight support display supported). TSSOP, 64-pinspackage Main Clock CK540 Integrated CK-SSCD and clock expansion buffer. ATA/Storage PATA66/100 One desktop PATA connector 4 back panel connectors • Ports [1:0] and [4:3] 3 cable-up
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Crown Beach Board Feature Crown Beach Board Comments Implementation 2 connectors. Mini Card connector A, PCI Express* functionality is enabled by NOTE: For more information, refer to Mini Card default. Section 2.5.4, PCI Express* connector Slots. NOTE: PCI Express* signals are left unconnected on Mini Card B. LPC One LPC slot No DMA support TPM Through TPM header (TPM 1.2) Microcontroller Renesas Technology* H8S/2117 Includes integrated SPI as an option FWH FWH LPC
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Crown Beach Board 2.5 Subsystem Descriptions Subsystem features refer to the socket and connector locations on the Crown Beach Board. Socket and connector locations are labeled with a letter-number combination. Refer to the silkscreen labeling on Crown Beach Board for location detail. 2.5.1 Intel® SCH Chipset • Processor interface at 400/533 MHz • Single channel DDR2 memory interface running at 400/533 MT/s • Two PCI Express* ports, x1 • Eight USB 2.0 compatible ports • One A
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Crown Beach Board Table 4. Crown Beach Supported LVDS Displays Manufacturer Size Resolution Back Aspect Part# /Type Light Ratio 4.8 inch Samsung (121.92 mm) 1024 x 600 11 LED 16 x 9 LTS480WS-C01 5.6 inch TMD (142.24 mm) 1024 x 600 CCFL 16 x 9 LTD056ET0S 7.2 inch Sharp (182.88 mm) 1280 x 768 32 LED 15 x 9 LQ072K1LA08 15 inch Samsung (381.00 mm) 1024 x 768 CCFL 4 x 3 LTN150XG-L08 8.4 inch NEC (213.36 mm) 640 x 480 2 CCFL 4 x 3 NL6448BC26-08D 9.0 inch NEC (228.
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Crown Beach Board Crown Beach. The Mott Canyon 4 card is required to enable the High Definition Audio functionality. See Appendix A for more information on the Mott Canyon 4 card. 2.5.6 PATA Storage The Crown Beach Board provides only one desktop, 40-pin, PATA66/100 connector that supports master and slave devices. 2.5.7 USB Connectors The Intel® SCH provides eight USB 2.0 ports. • Four ports are routed to the back panel’s two stacked USB connectors. USB ports [1:0] and [4:3]
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Crown Beach Board • Two PS/2 ports. Note: The two PS/2 ports are for a legacy keyboard and mouse. The keyboard plugs into the bottom port and the mouse plugs into the top port. • EMA support • Wake/runtime SCI events • Power sequencing control 2.5.10 EFI Firmware Hub (FWH) A TSOP socket houses the flash device (ST Microelectronics P/N# M50FW080) that stores the system EFI firmware. The EFI firmware can be programmed through a Microsoft MS-DOS* or Windows*-based utility. 2.5
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Crown Beach Board 2.5.15 In-Target Probe (ITP) and Debug Support Crown Beach provides on-board ITP support with an XDP connector. Users can debug from the reset vector without EFI or OS dependency (up to OS functionality). Ports 80-83 are provided as a troubleshooting tool to monitor POST output during EFI execution. Note: ITP requires that the CMC load to configure Poulsbo before register accesses can be made. The CMC code resides in the FWH on Crown Beach. Thus, it is required
