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MPR603HSU-03 MPC603EC/D
(IBM Order Number) (Motorola Order Number)
5/95
REV 2
™
Advance Information
™
PowerPC 603 RISC Microprocessor
Hardware Specifications
The PowerPC 603 microprocessor is an implementation of the PowerPC™ family of
reduced instruction set computer (RISC) microprocessors. This document contains
pertinent physical characteristics of the 603. For functional characteristics of the processor,
refer to the PowerPC 603 RISC Microprocessor User’s Manual.
This d
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1.1 Overview The 603 is the first low-power implementation of the PowerPC microprocessor family of RISC microprocessors. The 603 implements the 32-bit portion of the PowerPC Architecture™ specification, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floating-point data types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC architecture provides 64-bit integer data types, 64-bit addressing, and other features required to complete t
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• Five independent execution units and two register files — BPU featuring static branch prediction — A 32-bit IU — Fully IEEE 754-compliant FPU for both single- and double-precision operations — LSU for data transfer between data cache and GPRs and FPRs — SRU that executes condition register (CR) and special-purpose register (SPR) instructions — Thirty-two GPRs for integer operands — Thirty-two FPRs for single- or double-precision operands • High instruction and data throughput — Zero-cycle
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1.2 General Parameters The following list provides a summary of the general parameters of the 603. Technology 0.5 m CMOS (four-layer metal) Die size 11.5 mm x 7.4 mm Transistor count 1.6 million Logic design Fully-static Max. internal frequency 80 MHz Max. bus frequency 66.67 MHz Package Surface mount, 240-pin CQFP Power supply 3.3 – 5% V dc For ordering information, refer to Section 1.8, “Ordering Information.” 1.3 Electrical and Thermal Characteristics T
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Table 3 provides the DC electrical characteristics for the 603. Table 3. DC Electrical Specifications Vdd = 3.3 – 5% V dc, GND = 0 V dc, 0 £ T £ 105 C j Characteristic Symbol Min Max Unit Input high voltage (all inputs except SYSCLK) V 2.2 5.5 V IH Input low voltage (all inputs except SYSCLK) V GND 0.8 V IL SYSCLK input high voltage CV 2.4 5.5 V IH SYSCLK input low voltage CV GND 0.4 V IL 1 Input leakage current, V = 3.465
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Table 4. Power Dissipation (Continued) Vdd = 3.3 – 5% V dc, GND = 0 V dc, 0 £ T £ 105 C j Bus Frequency (SYSCLK) CPU Clock: Unit SYSCLK 25 MHz 33 MHz 40 MHz 50 MHz 66 MHz 1 Nap Mode 1:1 Typical 160 mW 2:1 Typical 140 160 mW 1 Sleep Mode 1:1 Typical 125 mW 2:1 Typical 110 130 mW 1 Sleep Mode—PLL Disabled 1:1 Typical 70 mW 2:1 Typical 30 40 mW 1 Sleep Mode—PLL and SYSCLK Disabled 1:1 Typical 2.0 mW 2:1 Typical 2.0 2.0 mW Note: 1. The values pro
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Table 5. Clock AC Timing Specifications (Continued) Vdd = 3.3 – 5% V dc, GND = 0 V dc, 0 £ T £ 105 C J 25 MHz 33.33 MHz 40 MHz 50 MHz 66.67 Num Characteristic Unit Notes Min Max Min Max Min Max Min Max Min Max 8 SYSCLK — – 150 — – 150 — – 150 — – 150 — – 150 ps 2 short- and long-term jitter 9 603 internal — 100 — 100 — 100 — 100 — 100 m s 3,4 PLL relock time Notes: 1. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V. 2. This is
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Table 6. Input AC Timing Specifications Vdd = 3.3 – 5% V dc, GND = 0 V dc, 0 £ T £ 105 C J 25 MHz 33.33 MHz 40 MHz 50 MHz 66.67 MHz Unit Num Characteristic Notes Min Max Min Max Min Max Min Max Min Max 10a Address/data/transfer 4.5 — 4.0 — 3.5 — 3.0 — 2.5 — ns 2 attribute inputs valid to SYSCLK (input setup) 10b All other inputs valid 6.5 — 6.0 — 5.5 — 5.0 — 4.5 — ns 3 to SYSCLK (input setup) 10c Mode select inputs 8 * — 8 * — 8 * — 8 * — 8 * — ns 4,5, valid to HRESET t t t t t 6,7 sys sys
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SYSCLK VM 10a 10b 11a 11b ALL INPUTS VM = Midpoint Voltage (1.4V) Figure 2. Input Timing Diagram VM HRESET 10c 11c MODE PINS VM = Midpoint Voltage (1.4 V) Figure 3. Mode Select Input Timing Diagram 1.3.2.3 Output AC Specifications Table 7 provides the output AC timing specifications for the 603 (shown in Figure 4). These specifications are for 25, 33.33, 40, 50, and 66.67 MHz bus clock (SYSCLK) frequencies. Table 7. Output AC Timing Specifications Vdd = 3.3 – 5% V dc, GND = 0 V dc, C = 50 p
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Table 7. Output AC Timing Specifications (Continued) Vdd = 3.3 – 5% V dc, GND = 0 V dc, C = 50 pF, 0 £ T £ 105 C L J 25 33.33 40 50 66.67 Num Characteristic Unit Notes Min Max Min Max Min Max Min Max Min Max 14a SYSCLK to output — 16.0 — 15.0 — 14.0 — 13.0 — 12.0 ns 4 valid (5.5 V to 0.8 V— all except TS, ABB, ARTRY, DBB ) 14b SYSCLK to output — 14.0 — 13.0 — 12.0 — 11.0 — 10.0 ns 6 valid (all except TS, ABB, ARTRY, DBB) 15 SYSCLK to output 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns 3 invalid (out
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VM VM VM SYSCLK 14 15 16 12 ALL OUTPUTS (Except TS, ABB DBB, ARTRY) 13 15 13 16 TS 17 ABB, DBB 21 20 19 18 ARTRY VM = Midpoint Voltage (1.4 V) Figure 4. Output Timing Diagram 603 Hardware Specifications, REV 2 11 Preliminary—Subject to Change without Notice
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1.3.3 JTAG AC Timing Specifications Table 8 provides the JTAG AC timing specifications. Table 8. JTAG AC Timing Specifications (Independent of SYSCLK) Vdd = 3.3 – 5% V dc, GND = 0 V dc, C = 50 pF, 0 £ T £ 105 C L J Num Characteristic Min Max Unit Notes TCK frequency of operation 0 16 MHz 1 TCK cycle time 62.5 — ns 2 TCK clock pulse width measured at 1.4 V 25 — ns 3 TCK rise and fall times 0 3 ns 4 TRST setup time to TCK rising edge 13 — ns 1 5 TRST assert time 40 — ns 6 Boundary-scan input dat
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Figure 6 provides the TRST timing diagram. TCK 4 TRST 5 Figure 6. TRST Timing Diagram Figure 7 provides the boundary-scan timing diagram. TCK 6 7 Data Inputs Input Data Valid 8 Data Outputs Output Data Valid 9 Data Outputs 8 Data Outputs Output Data Valid Figure 7. Boundary-Scan Timing Diagram Figure 8 provides the test access port timing diagram. TCK 10 11 TDI, TMS Input Data Valid 12 TDO Output Data Valid 13 TDO 12 TDO Output Data Valid Figure 8. Test Access Port Timing Diagram 603 Hardware S
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1.4 Pinout Diagram Figure 9 contains the pin assignments for the 603. GBL 1 180 TT4 A1 2 179 A0 A3 178 A2 3 VDD 177 VDD 4 1 A5 5 176 A4 A7 6 175 A6 A9 174 A8 7 OGND 173 OVDD 8 GND 9 172 GND OVDD 10 171 OGND A11 170 A10 11 A13 12 169 A12 A15 13 168 A14 VDD 14 167 VDD A17 166 A16 15 A19 16 165 A18 TOP VIEW A21 17 164 A20 OGND 18 163 OVDD GND 162 GND 19 OVDD 20 161 OGND A23 21 160 A22 A25 22 159 A24 A27 158 A26 23 VDD 24 157 VDD DBWO 25 156 DRTRY DBG 155 TA 26 BG 154 TEA 27 AACK 28 153 DBDIS GND 2
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1.5 Pinout Listing Table 9 provides the pinout listing for the 603. Table 9. PowerPC 603 Microprocessor Pinout Listing Signal Name Pin Number Active I/O A0–A31 179, 2, 178, 3, 176, 5, 175, 6, 174, 7, 170, High I/O 11, 169, 12, 168, 13, 166, 15, 165, 16, 164, 17, 160, 21, 159, 22, 158, 23, 151, 30, 144, 37 AACK 28 Low Input ABB 36 Low I/O AP0–AP3 231, 230, 227, 226 High I/O APE 218 Low Output ARTRY 32 Low I/O AVDD 209 High Input BG 27 Low Input BR 219 Low Output CI 237 Low Output CLK_OUT 221
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Table 9. PowerPC 603 Microprocessor Pinout Listing (Continued) Signal Name Pin Number Active I/O HRESET 214 Low Input INT 188 Low Input 1 LSSD_MODE 205 Low Input 1 L1_TSTCLK 204 — Input 1 L2_TSTCLK 203 — Input MCP 186 Low Input OGND 8, 18, 33, 43, 53, 60, 69, 77, 86, 95, 103, Low Input 111, 120, 127, 136, 146, 161, 171, 181, 193, 220, 228, 238 OVDD 10, 20, 35, 45, 54, 61, 70, 79, 88, 96, 104, High Input 112, 121, 128, 138, 148, 163, 173, 183, 194, 222, 229, 240 PLL_CFG0–PLL_CFG3 213, 211, 210,
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Table 9. PowerPC 603 Microprocessor Pinout Listing (Continued) Signal Name Pin Number Active I/O TS 149 Low I/O TT0–TT4 191, 190, 185, 184, 180 High I/O VDD 4, 14, 24, 34, 44, 59, 122, 137, 147, 157, High Input 167, 177, 207 WT 236 Low Output XATS 150 Low I/O Notes: 1. These are test signals for factory use only and must be pulled up to VDD for normal machine operation. 2. OVDD inputs supply power to the I/O drivers and VDD inputs supply power to the processor core. Future members of the 603 fa
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1.6.1.2 Mechanical Dimensions of the Motorola Wire-Bond CQFP Package Figure 10 shows the mechanical dimensions for the wire-bond CQFP package. AB q I R –H– q 2 R H G AA F C A J B *Reduced pin count shown for clarity. 60 pins per side Min. Max. A 30.86 31.75 B 34.6 BSC C 3.75 4.15 D 0.5 BSC E 0.18 0.30 F 3.10 3.90 G 0.13 0.175 H 0.45 0.55 J 0.25 – AA 1.80 REF AB 0.95 REF q12 6 q21 7 R 0.15 REF Pin 240 Pin 1 Notes: 1. BSC—Between Standard Centers. 2. All measurements in mm. DE Die Wire Bonds
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1.6.2 IBM C4-CQFP Package Description The following sections provide the package parameters and mechanical dimensions for the IBM C4-CQFP package. 1.6.2.1 Package Parameters The package parameters are as provided in the following list. The package type is 32 mm x 32 mm, 240-pin ceramic quad flat pack. Package outline 32 mm x 32 mm Interconnects 240 Pitch 0.5 mm Lead plating Ni Au Solder joint Sn/PB (10/90) Lead encapsulation Epoxy Solder-bump encapsulation Epoxy Maximum module height 3.1 mm Co-
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1.6.2.2 Mechanical Dimensions of the IBM C4-CQFP Package Figure 11 shows the mechanical dimensions for the C4-CQFP package. Epoxy Dam Solder-Bump Encapsulant Chip F Rad Ang G Jmin Urethane Clip Leadframe Tape Cast Ceramic H Cmax C- 0.08 A s 0.13 TOTAL A-B *Reduced pin count shown for clarity. 60 pins per side E Min. Max. A 31.8 32.2 B 34.4 34.8 -B- C 3.05 3.15 D 0.45 0.55 E 0.18 0.28 D 0.08 TOTAL M A-B Pin 240 Pin 1 -A- B * Not to scale s 0.13 TOTAL A-B All measurements in mm Figure 11. Mechani
