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Digital Processor / Digital Mixer
SERVICE MANUAL
Models:
IQ-USM 810
®
Some models may be exported under the name Amcron.
©2000 by Crown International, Inc., P.O. Box 1000, Elkhart, Indiana 46515-1000 U.S.A.
Telephone: 219-294-8000. Trademark Notice: Distributed Intelligence™ and IQ for Windows™
® ® ®
are trademarks and Crown , IQ , and IQ System are registered trademarks of Crown
International, Inc. Other trademarks are the property of their respective owners.
130447-1
04-00
Rev. A
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130447-1 Rev. A IQ-USM 810 Service Manual The information furnished in this manual does not include all of the details of design, production, or variations of the equipment. Nor does it cover every possible situation which may arise during installation, operation or maintenance. If you need special assistance beyond the scope of this manual, please contact the Crown Technical Support Group. Mail: P.O. Box 1000 Elkhart IN 46515-1000 Shipping: Plant 2 SW 1718 W. Mishawaka Road Elkhart IN
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IQ-USM 810 Service Manual 130447-1 Rev. A Revision History Comments Revision Number Date Rev. A 04-2000 Initial Printing III ©2000 Crown International, Inc.
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130447-1 Rev. A IQ-USM 810 Service Manual This page intentionally left blank IV ©2000 Crown International, Inc.
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IQ-USM 810 Service Manual 130447-1 Rev. A Table of Contents 1 Introduction ............................................................................ 1-1 1.1 Introduction ................................................................................ 1-1 1.2 The IQ-USM 810 ........................................................................ 1-1 1.3 Warranty ..................................................................................... 1-1 2 Specifications ..........................
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130447-1 Rev. A IQ-USM 810 Service Manual Table of Contents 4.5 Standard Initial Conditions ........................................................ 4-2 4.6 Test Procedures ......................................................................... 4-2 4.7 Typical Measurements ............................................................... 4-7 4.8 Test/Debug Objects ................................................................... 4-7 4.9 Display Test Patterns ..................................
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130447-1 Rev. A IQ-USM 810 Service Manual Outputs and eight AUX Audio Outputs. The Main and AUX Audio Output sections further process the sig- 1 Introduction nal with individually adjustable signal delay and fil- ters along with an Ambient-Leveler and a high perfor- mance Output Limiter for system protection. 1.1 Introduction A Multi-Function Control Port implements analog and This manual contains complete service information ® digital I/O for control and monitor by simple potenti- on the Crown
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130447-1 Rev. A IQ-USM 810 Service Manual Figure 1.1 IQ-USM 810 Front and Rear Views 1-2 Introduction ©2000 Crown International, Inc.
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130447-1 Rev. A IQ-USM 810 Service Manual 1 stop bit; 8 data bits; no parity. Crown Bus Interface Type: Optically isolated 20 mA 2 Specifications current loop. Operation: Half-duplex. General Transmission Distance: Variable from 200 to 3000 Front Panel Controls: Front-panel switches select IQ feet (61 to 914 meters), depending upon wire capaci- Address, Baud Rate, factory default preset (P00), and tance. Typically 1000 feet (305 meters) using shielded any of 32 user-defined presets (P01–P32). tw
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130447-1 Rev. A IQ-USM 810 Service Manual This page intentionally left blank 2-2 Specifications ©2000 Crown International, Inc.
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130447-1 Rev. A IQ-USM 810 Service Manual 3.3 Input 3 Circuit Theory The input Printed Wire Assembly (PWA) is located at the back of the unit on the bottom. It offers eight bal- anced input audio channels via 3 pin connectors. Fig- ure 3.2 shows the block diagram of the input PWA. The 3.1 Overview PWA is composed of the following sections: Input Ana- This section explains operation of the IQ-USM 810 cir- log Processing, Clock Signals, A/D Conversion, and DC cuitry. Please refer to the IQ-USM 81
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130447-1 Rev. A IQ-USM 810 Service Manual Figure 3.2 Input PWA Block Diagram • Line: In Line mode, both the coupling capacitors generates a 12.288 MHz signal (256Fs). This clock is (C104 & C105) and the series resistors (R103 & buffered by U3 and provides separate outputs to each R104) are in the signal path. The capacitors block of the A/D converters, the Output PWA for the DAC's, the phantom voltage from the input while the se- and to the SHARC PWA for distribution to the optional ries resisto
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130447-1 Rev. A IQ-USM 810 Service Manual Figure 3.3 Input Analog Processing Circuitry (one channel) Circuit Theory 3-3 ©2000 Crown International, Inc.
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130447-1 Rev. A IQ-USM 810 Service Manual Figure 3.4 Audio Data and Clock Signals 2 used. This data is routed to the SHARC PWA for pro- Each DAC takes a 2 channel I S 32-bit time-division cessing (ADC1-4). Figure 3.4 shows the audio data and multiplexed data audio stream from the SHARC PWA its relationship to the clock signals. and converts it at a 24-bit, 48-kHz rate (Figure 3.4). Like the A/D converter, the audio output of the DAC is bi- 3.3.4 DC Voltages ased positive by 2.2V and a full signa
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130447-1 Rev. A IQ-USM 810 Service Manual Figure 3.6 Output Analog Processing Circuitry (one channel) ceives commands from the System Controller (SH_A0- 3.5 SHARC Processing 2, \HCS, HR/W) to load data and addresses into these The SHARC PWA sits in the center of the chassis and is latches. Once the data is in the latches, U23 communi- the DSP engine that provides all of the signal process- cates with Arbiter PLD U24 (\SYSBR, \SYSBG, \RD, \WR) ing for the unit. At the core of this processing is f
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130447-1 Rev. A IQ-USM 810 Service Manual Figure 3.8 SHARC PWA Block Diagram The System Controller will display the error code, then 3.5.7 Bus Utilization begin the boot process again. By watching the boot The Arbiter PLD also works with the Bus Utilization PLD, process on the front display, the error code can be read U30, to monitor each SHARC processor and determine at the end of the boot process before the next boot be- how much of the available SHARC bus bandwidth each gins. is using. The Ar
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130447-1 Rev. A IQ-USM 810 Service Manual Figure 3.9 SHARC Pinout The time allotted for the SHARC to process this audio • A/D Conversion 667us data is 330us (16 samples x 48-kHz). At that point the • 5x "brick" delay 1667us next audio brick has been collected and is ready for • DAC Conversion 520us processing. The processed output audio brick is then deposited into SRAM (U5, U6). The audio bricks are • Total Delay 2854us then taken by the Output SHARC's for mixing and out- This delay is constant
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130447-1 Rev. A IQ-USM 810 Service Manual bus and accesses SDRAM when it is available. The nected. If CNET is available, the CNET PWA is respon- SHARC blocks access to the bus through the use of sible to provide the Serial and Frame Clocks. The PLD the \SDLOCK pin during SDRAM transfers. SDRAM is accepts the CNET audio clocks and routes them to the utilized only for audio delay processing and has no firm- SHARC's and Input PWA. If the CNET PWA is not con- ware. If audio is available at the input
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130447-1 Rev. A IQ-USM 810 Service Manual HC12. The clock is buffered by U5D and is provided to 3.6.1 Control Processing dual UART U2 for baud rate creation. The brain of the System Controller PWA is the Motorola 68HC12 microcontroller, U15. The 112pin QFP pinout When the HC12 comes out of reset, it looks to the flash is shown in Figure 3.11. memory (U13) and begins its boot process. Due to the slow response of flash memory, normal code process- The HC12 has a Background Debug Mode (BDM) con- in
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130447-1 Rev. A IQ-USM 810 Service Manual The HC12 firmware uses a real time operating system RTC_CS (chip select) and periodically queries the RTC (RTOS) to make efficient use of the HC12's processing to get or set the time. capability. Various tasks are given priorities, and the Capacitor C25 is a 1F supercap that allows the RTC to RTOS supervises what task has control of the proces- continue to keep time after the unit is powered down. sor at any particular time. The RTC senses the loss of po
