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TMS320DM36x Digital Media System-on-Chip
(DMSoC)
Ethernet Media Access Controller (EMAC)
User's Guide
Literature Number: SPRUFI5B
March 2009–Revised December 2010
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2 SPRUFI5B–March 2009–Revised December 2010 Submit Documentation Feedback © 2009–2010, Texas Instruments Incorporated
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Preface ...................................................................................................................................... 10 1 Introduction ...................................................................................................................... 13 1.1 Purpose of the Peripheral ............................................................................................. 13 1.2 Features .............................................................................
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www.ti.com 4.1 MDIO Version Register (VERSION) ................................................................................. 70 4.2 MDIO Control Register (CONTROL) ................................................................................ 71 4.3 PHY Acknowledge Status Register (ALIVE) ....................................................................... 72 4.4 PHY Link Status Register (LINK) .................................................................................... 72 4.5 M
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www.ti.com 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) .............................................. 115 5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) .............................................. 115 5.37 MAC Hash Address Register 1 (MACHASH1) ................................................................... 116 5.38 MAC Hash Address Register 2 (MACHASH2) ................................................................... 116 5.39 Back Off Test Register (BOFFTEST)
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www.ti.com List of Figures 1 EMAC and MDIO Block Diagram........................................................................................ 14 2 Ethernet Configuration MII Connections................................................................................ 16 3 Ethernet Frame Format................................................................................................... 18 4 Basic Descriptor Format.............................................................................
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www.ti.com 48 Transmit Interrupt Mask Set Register (TXINTMASKSET) ........................................................... 92 49 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) ..................................................... 93 50 MAC Input Vector Register (MACINVECTOR) ........................................................................ 94 51 MAC End Of Interrupt Vector Register (MACEOIVECTOR)......................................................... 94 52 Receive Interrupt
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www.ti.com List of Tables 1 EMAC and MDIO Signals for MII Interface............................................................................. 17 2 Ethernet Frame Description.............................................................................................. 18 3 Basic Descriptor Description............................................................................................. 20 4 Receive Frame Treatment Summary .................................................................
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www.ti.com 46 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions ..................................... 92 47 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions............................... 93 48 MAC Input Vector Register (MACINVECTOR) Field Descriptions.................................................. 94 49 MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions................................... 94 50 Receive Interrupt Status (Unmask
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Preface SPRUFI5B–March 2009–Revised December 2010 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the TMS320DM36x Digital Media System-on-Chip (DMSoC). Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and the registers descri
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www.ti.com Related Documentation From Texas Instruments SPRUFH2 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Asynchronous Receiver/Transmitter (UART) Users Guide This document describes the universal asynchronous receiver/transmitter (UART) peripheral in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The UART peripheral performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data received from the CPU. SPRUFH3
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Related Documentation From Texas Instruments www.ti.com SPRUFI5 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Ethernet Media Access Controller (EMAC) User's Guide This document describes the operation of the ethernet media access controller interface in the TMS320DM36x Digital Media System-on-Chip (DMSoC). SPRUFI7 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Analog to Digital Converter (ADC) User's Guide This document describes the operation of the analog to digital conversion in the
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User's Guide SPRUFI5B–March 2009–Revised December 2010 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 1 Introduction This document provides a functional description of the Ethernet Media Access Controller (EMAC) and physical layer (PHY) device Management Data Input/Output (MDIO) module integrated in the device. Included are the features of the EMAC and MDIO modules, a discussion of their architecture and operation, how these modules connect to the outside world, and
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Introduction www.ti.com • Emulation support • Loopback mode 1.3 Functional Block Diagram Figure 1 shows the three main functional modules of the EMAC/MDIO peripheral: • EMAC control module • EMAC module • MDIO module The EMAC control module is the main interface between the device core processor and the EMAC module and MDIO module. The EMAC control module contains the necessary components to allow the EMAC to make efficient use of device memory, plus it controls device interrupts. The EMAC contr
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www.ti.com Architecture The EMAC and MDIO interrupts are combined within the control module, so only the control module interrupt needs to be monitored by the application software or device driver. The EMAC control module combines the EMAC and MDIO interrupts and generates 4 separate interrupts to the ARM through the ARM interrupt controller. See Section 2.17.4 for details of interrupt multiplex logic of the EMAC control module. 1.4 Industry Standard(s) Compliance Statement The EMAC peripheral c
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Architecture www.ti.com 2.2 Memory Map The EMAC peripheral includes internal memory that is used to hold information about the Ethernet packets received and transmitted. This internal RAM is 2K × 32 bits in size. Data can be written to and read from the EMAC internal memory by either the EMAC or the CPU. It is used to store buffer descriptors that are 4-words (16-bytes) deep. This 8K local memory holds enough information to transfer up to 512 Ethernet packets without CPU intervention. The packet
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www.ti.com Architecture Table 1. EMAC and MDIO Signals for MII Interface Signal Type Description EMAC_TX_CLK I Transmit clock (EMAC_TX_CLK). The transmit clock is a continuous clock that provides the timing reference for transmit operations. The EMAC_TXD and EMAC_TX_EN signals are tied to this clock. The clock is generated by the PHY and is 2.5 MHz at 10 Mbps operation and 25 MHz at 100 Mbps operation. EMAC_TXD[3-0] O Transmit data (EMAC_TXD). The transmit data pins are a collection of 4 data si
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Architecture www.ti.com 2.5 Ethernet Protocol Overview Ethernet provides an unreliable, connection-less service to a networking application. A brief overview of the Ethernet protocol is given in the following subsections. For in-depth information on the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method, which is the Ethernet’s multiple access protocol, see the IEEE 802.3 standard document. 2.5.1 Ethernet Frame Format All the Ethernet technologies use the same frame s
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www.ti.com Architecture 2.5.2 Ethernet’s Multiple Access Protocol Nodes in an Ethernet Local Area Network are interconnected by a broadcast channel, as a result, when an EMAC port transmits a frame, all the adapters on the local network receive the frame. Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms are used when the EMAC operates in half-duplex mode. When operating in full-duplex mode, there is no contention for use of a shared medium, since there are exactly two
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Architecture www.ti.com Table 3. Basic Descriptor Description Word Offset Field Field Description 0 Next Descriptor The next descriptor pointer is used to create a single linked list of descriptors. Each descriptor Pointer describes a packet or a packet fragment. When a descriptor points to a single buffer packet or the first fragment of a packet, the start of packet (SOP) flag is set in the flags field. When a descriptor points to a single buffer packet or the last fragment of a packet, the end
