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TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
www.ti.com
SPRS268E–MAY 2005–REVISED JANUARY 2007
1 TMS320C6727, TMS320C6726, TMS320C6722 DSPs
1.1 Features
• C672x: 32-/64-Bit 300-MHz Floating-Point DSPs • Three Multichannel Audio Serial Ports
– Transmit/Receive Clocks up to 50 MHz
• Upgrades to C67x+ CPU From C67x™ DSP
– Six Clock Zones and 16 Serial Data Pins
Generation:
– Supports TDM, I2S, and Similar Formats
– 2X CPU Registers [64 General-Purpose]
– DIT-Capabl
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TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E–MAY 2005–REVISED JANUARY 2007 1.2 Description The TMS320C672x is the next generation of Texas Instruments' C67x generation of high-performance 32-/64-bit floating-point digital signal processors. The TMS320C672x includes the TMS320C6727, (1) TMS320C6726, and TMS320C6722 devices. Enhanced C67x+ CPU. The C67x+ CPU is an enhanced version of the C67x CPU used on the C671x DSPs. It is compatible with th
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TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E–MAY 2005–REVISED JANUARY 2007 The C6727 extends SDRAM support to 256M-bit and 512M-bit devices. Asynchronous memory support is typically used to boot from a parallel non-multiplexed NOR flash device that can be 8, 16, or 32 bits wide. Booting from larger flash devices than are natively supported by the dedicated EMIF address lines is accomplished by using general-purpose I/O pins for upper address
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TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E–MAY 2005–REVISED JANUARY 2007 Real-Time Interrupt Timer (RTI). The real-time interrupt timer module includes: • Two 32-bit counter/prescaler pairs • Two input captures (tied to McASP direct memory access [DMA] events for sample rate measurement) • Four compares with automatic update capability • Digital Watchdog (optional) for enhanced system robustness Clock Generation (PLL and OSC). The C672x DSP
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TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E–MAY 2005–REVISED JANUARY 2007 1.3 Functional Block Diagram Figure 1-1 shows the functional block diagram of the C672x device. Program/Data JTAG EMU 256 RAM D1 256K Bytes McASP0 Data 64 32 16 Serializers R/W C67x+ CPU 32 Program/Data D2 256 ROM Page0 Memory Data 64 Controller 256K Bytes 32 R/W McASP1 6 Serializers 32 Program Program/Data I/O INT Fetch 256 ROM Page1 32 McASP2 128K Bytes 2 Serializers
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TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E–MAY 2005–REVISED JANUARY 2007 Contents 1 TMS320C6727, TMS320C6726, TMS320C6722 4.3 Recommended Operating Conditions............... 33 DSPs........................................................ 1 4.4 Electrical Characteristics ............................ 34 1.1 Features .............................................. 1 4.5 Parameter Information .............................. 35 1.2 Description....
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TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E–MAY 2005–REVISED JANUARY 2007 2 Device Overview 2.1 Device Characteristics Table 2-1 provides an overview of the C672x DSPs. The table shows significant features of each device, including the capacity of on-chip memory, the peripherals, the execution time, and the package type with pin count. Table 2-1. Characteristics of the C672x Processors HARDWARE FEATURES C6727 C6726 C6722 dMAX 1 EMIF 1 (32-bi
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TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E–MAY 2005–REVISED JANUARY 2007 2.2 Enhanced C67x+ CPU The TMS320C672x floating-point digital signal processors are based on the new C67x+ CPU. This core is code-compatible with the C67x CPU core used on the TMS320C671x DSPs, but with significant (2) enhancements including an increase in core operating frequency from 225 MHz to 300 MHz while operating at 1.2 V. The CPU fetches 256-bit-wide advanced v
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TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E–MAY 2005–REVISED JANUARY 2007 Table 2-2. New Floating-Point Instructions for C67x+ CPU FLOATING-POINT INSTRUCTION IMPROVES (1) OPERATION MPYSPDP SP x DP → DP Faster than MPYDP. Improves high Q biquads (bass management) and FFT. MPYSP2DP SP x SP → DP Faster than MPYDP. Improves Long FIRs (EQ). ADDSP (new to CPU “S” Unit) SP + SP → SP ADDDP (new to CPU “S” Unit) DP + DP → DP Now up to four floating-p
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TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E–MAY 2005–REVISED JANUARY 2007 2.4 Internal Program/Data ROM and RAM The organization of program/data ROM and RAM on C672x is simple and efficient. ROM is organized as two 256-bit-wide pages with four 64-bit-wide banks. RAM is organized as a single 256-bit-wide page with eight 32-bit-wide banks. The internal memory organization is illustrated in Figure 2-2 (ROM) and Figure 2-3 (RAM). ROM Page 1 Base
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TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E–MAY 2005–REVISED JANUARY 2007 2.5 Program Cache The C672x DSP executes code directly from a large on-chip 32K-byte program cache. The program cache has these key features: • Wide 256-bit path to internal ROM/RAM • Single-cycle access on cache hits • 2-cycle miss penalty to internal ROM/RAM • Caches external memory as well as ROM/RAM • Direct-mapped • Modes: Enable, Freeze, Bypass • Software invalid
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TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E–MAY 2005–REVISED JANUARY 2007 2.6 High-Performance Crossbar Switch The C672x DSP includes a high-performance crossbar switch that acts as a central hub between bus masters and targets. Figure 2-4 illustrates the connectivity of the crossbar switch. Program ROM RAM CPU PLL RTI SPI0 SPI1 I2C0 I2C1 EMIF Cache External Memory Controller Memory T2 SDRAM/ Data CPU Program Flash Master Slave Master Periph
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TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E–MAY 2005–REVISED JANUARY 2007 The five bus masters arbitrate for five different target groups: T1 On-chip memories through the CPU Slave Port (CSP). T2 Memories on the external memory interface (EMIF). T3 Peripheral registers through the peripheral configuration bus. T4 McASP serializers through the dedicated McASP DMA bus. T5 dMAX registers. The crossbar switch supports parallel accesses from diff
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TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E–MAY 2005–REVISED JANUARY 2007 Figure 2-5 shows the bit layout of the device-level bridge control register (CFGBRIDGE) and Table 2-7 contains a description of the bits. 31 16 Reserved 15 1 0 Reserved CSPRST R/W, 1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 2-5. CFGBRIDGE Register Bit Layout (0x4000 0024) Table 2-7. CFGBRIDGE Register Bit Field Description (0x4000 0024) BI
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TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E–MAY 2005–REVISED JANUARY 2007 2.7 Memory Map Summary A high-level memory map of the C672x DSP appears in Table 2-8. The base address of each region is listed. Any address past the end address must not be read or written. The table also lists whether the regions are word-addressable or byte- and word-addressable. Table 2-8. C672x Memory Map DESCRIPTION BASE ADDRESS END ADDRESS BYTE- OR WORD-ADDRESSA
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TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E–MAY 2005–REVISED JANUARY 2007 2.8 Boot Modes The C672x DSP supports only one hardware bootmode option, this is to boot from the internal ROM starting at address 0x0000 0000. Other bootmode options are implemented by a software bootloader stored in ROM. The software bootloader uses the CFGPIN0 and CFGPIN1 registers, which capture the state of various device pins at reset, to determine which mode to
Resumo do conteúdo contido na página número 17
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E–MAY 2005–REVISED JANUARY 2007 Figure 2-6 shows the bit layout of the CFGPIN0 register and Table 2-10 contains a description of the bits. 31 8 Reserved 7 6 5 4 3 2 1 0 PINCAP7 PINCAP6 PINCAP5 PINCAP4 PINCAP3 PINCAP2 PINCAP1 PINCAP0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 2-6. CFGPIN0 Register Bit Layout (0x4000 0000) Table 2-10. CFGPIN0 Register Bit Field Description (
Resumo do conteúdo contido na página número 18
TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E–MAY 2005–REVISED JANUARY 2007 Figure 2-7 shows the bit layout of the CFGPIN1 register and Table 2-11 contains a description of the bits. 31 8 Reserved 7 6 5 4 3 2 1 0 PINCAP15 PINCAP14 PINCAP13 PINCAP12 PINCAP11 PINCAP10 PINCAP9 PINCAP8 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 2-7. CFGPIN1 Register Bit Layout (0x4000 0004) Table 2-11. CFGPIN1 Register Bit Field Descrip
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TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E–MAY 2005–REVISED JANUARY 2007 2.9 Pin Assignments 2.9.1 Pin Maps Figure 2-8 and Figure 2-9 show the pin assignments on the 256-terminal GDH/ZDH package and the 144-pin RFP package, respectively. '"' ! ! '" '% & '%& '%& ! '%& '%& ! '%& '% & ' ! ! %& '%& '"' '"' ! ' ' '%& '%& '%& '%& '%& '
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TMS320C6727, TMS320C6726, TMS320C6722 Floating-Point Digital Signal Processors www.ti.com SPRS268E–MAY 2005–REVISED JANUARY 2007 V 109 72 V SS SS SPI0_SIMO 110 71 EM_CKE SPI0_SOMI/I2C0_SDA 111 70 EM_CLK 112 69 DV V DD SS AXR0[0] 113 68 DV DD V 114 67 EM_WE_DQM[1] SS AXR0[1] 115 66 EM_D[8] AXR0[2] 116 65 CV DD 117 64 AXR0[3] EM_D[9] V 118 63 EM_D[10] SS AXR0[4] 119 62 V SS AXR0[5]/SPI1_SCS 120 61 EM_D[11] 121 60 AXR0[6]/SPI1_ENA DV DD AXR0[7]/SPI1_CLK 122 59 EM_D[12] CV 123 58 EM_D[13] DD V 124 5
