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TM
LogiCORE IP
Ethernet AVB
Endpoint v2.4
User Guide
UG492 July 23, 2010
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Xilinx is providing this product documentation, hereinafter “Information,” to you “AS IS” with no warranty of any kind, express or implied. Xilinx makes no representation that the Information, or any particular implementation thereof, is free from any claims of infringement. You are responsible for obtaining any rights you may require for any implementation based on the Information. All specifications are subject to change without notice. XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WI
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Table of Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Schedule of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Preface: About This Guide Guide Contents . . . . . . . . . . . .
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Chapter 4: Generating the Core Ethernet AVB GUI Page 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Component Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Core Delivery Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Ethernet AVB GUI Page 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 8: Real Time Clock and Time Stamping Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 RTC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Clock Outputs Based on the Synchronized RTC Nanoseconds Field . . . . . . . . . . . . . 79 Time Stamping Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 14: Quick Start Example Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Generating the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Implementing the Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Simulating the Example Design . . . . . . . . . . . . . . . .
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Chapter 16: Detailed Example Design (EDK format) Directory and File Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 / . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 /doc . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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8 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010
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Schedule of Figures Chapter 1: Introduction Chapter 2: Licensing the Core Chapter 3: Overview of Ethernet Audio Video Bridging Figure 3-1: Example AVB Home Network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 3-2: Example Ethernet AVB Endpoint System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Chapter 4: Generating the Core Figure 4-1: GUI Page 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 9: Precise Timing Protocol Packet Buffers Figure 9-1: Tx PTP Packet Buffer Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 9-2: Rx PTP Packet Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Chapter 10: Configuration and Status Figure 10-1: Single Read Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 10-2: Single Write T
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Chapter 16: Detailed Example Design (EDK format) Appendix A: RTC Time Stamp Accuracy Figure A-1: RTC Periodic Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Figure A-2: RTC Sampling Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Figure A-3: Sampling Position Uncertainty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Figure A-4: Overall Time Stamp
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12 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010
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Schedule of Tables Chapter 1: Introduction Chapter 2: Licensing the Core Chapter 3: Overview of Ethernet Audio Video Bridging Chapter 4: Generating the Core Table 4-1: XCO File Values and Default Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Chapter 5: Core Architecture Table 5-1: Clocks and Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 5-2: Legacy Traffic Signals: Transmitter Path .
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Table 10-7: Seconds Field Offset bits [31:0] (PLB_base_address + 0x2808) . . . . . . . . . . . . 95 Table 10-8: Seconds Field Offset bits [47:32] (PLB_base_address + 0x280C) . . . . . . . . . . 95 Table 10-9: RTC Increment Value Control Register (PLB_base_address + 0x2810). . . . . 95 Table 10-10: Current RTC Nanoseconds Value (PLB_base_address + 0x2814). . . . . . . . . 96 Table 10-11: Current RTC Seconds Field Value bits [31:0] (PLB_base_address + 0x2818) 96 Table 10-12: Current RTC Seco
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Chapter 16: Detailed Example Design (EDK format) Table 16-1: Project Directory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Table 16-2: Component Name Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Table 16-3: Doc Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Table 16-4: Driver Data Directory . . . . . . . . . .
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16 www.xilinx.com Ethernet AVB Endpoint User Guide UG492 July 23, 2010
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Preface About This Guide The LogiCORE™ IP Ethernet AVB User Guide provides information about the Ethernet Audio Video Bridging (AVB) Endpoint core, including how to customize, generate, and implement the core in supported Xilinx FPGA families. Guide Contents This guide contains the following chapters: • Preface, “About this Guide” introduces the organization and purpose of this guide and the conventions used in this document. • Chapter 1, “Introduction” introduces the core and provides relat
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Preface: About This Guide • Chapter 13, “Software Drivers” describes the function of the software drivers delivered with the core. • Chapter 14, “Quick Start Example Design”Chapter 3, “Quick Start Example Design” provides instructions to quickly generate the core and run the example design through implementation and simulation using the default settings. • Chapter 15, “Detailed Example Design (Standard Format)” provides detailed information about the core when generated in the standard CORE
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Conventions Convention Meaning or Use Example A list of items from which you Braces { } lowpwr ={on|off} must choose one or more Separates items in a list of Vertical bar | lowpwr ={on|off} choices User-defined variable or in code Angle brackets < > samples IOB #1: Name = QOUT’ Vertical ellipsis IOB #2: Name = CLKIN’ . Repetitive material that has . . been omitted . . . Repetitive material that has allow block block_name loc1 Horizontal ellipsis . . . been omitted
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Preface: About This Guide List of Abbreviations The following table describes acronyms used in this manual. Acronym Spelled Out AV Audio Video AVB Audio Video Bridging BMCA Best Master Clock Algorithm CRC Cyclic Redundancy Check DA Destination Address DMA Direct Memory Access DSP Digital Signal Processor EDK Embedded Development Kit EMAC Ethernet MAC FCS Frame Check Sequence FIFO First In First Out FPGA Field Programmable Gate Array. Gbps Gigabits per second GMII Gigabit Media Independent Interf
