Resumo do conteúdo contido na página número 1
CYV15G0404RB
Independent Clock Quad HOTLink II™
Deserializing Reclocker
and SMPTE 259 video applications. It supports signaling rates
Features
in the range of 195 to 1500 Mbps for each serial link. The four
®
• Second-generation HOTLink technology channels are independent and can simultaneously operate at
different rates. Each receive channel accepts serial data and
• Compliant to SMPTE 292M and SMPTE 259M video
converts it to 10-bit parallel characters and presents these
standards
characters
Resumo do conteúdo contido na página número 2
Video Coprocessor CYV15G0404RB Figure 1. HOTLink II™ System Connections Reclocked Outputs 10 10 10 Independent 10 Independent Channel Channel CYV15G0404RB CYV15G0403TB Serial Links 10 Reclocking Deserializer Serializer 10 10 10 Reclocked Outputs CYV15G0404RB Deserializing Reclocker Logic Block Diagram x10 x10 x10 x10 Deserializer Deserializer Deserializer Deserializer RX RX RX RX Reclocker Reclocker Reclocker Reclocker Document #: 38-02102 Rev. *C Page 2 of 27 [+] Feedback ROUTA1± ROUTA2± R
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CYV15G0404RB = Internal Signal Reclocking Deserializer Path Block Diagram RESET TRST TRGRATEA JTAG TMS x2 TRGCLKA Boundary TCLK Scan TDI Controller SDASEL[2..1]A[1:0] TDO LDTDEN LFIA Receive Signal INSELA Monitor 10 RXDA[9:0] 10 10 INA1+ INA1– Clock & BISTSTA INA2+ Data INA2– Recovery RXCLKA+ PLL ÷2 ULCA RXCLKA– SPDSELA RXBISTA[1:0] RXPLLPDA RXRATEA Recovered Serial Data Recovered Character Clock ROE[2..1]A Reclocker ROUTA1+ ROE[2..1]A ROUTA1– Output PLL Clock Multiplier A ROUTA2+ ROUTA2– RE
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CYV15G0404RB Reclocking Deserializer Path Block Diagram (continued) = Internal Signal TRGRATEC x2 TRGCLKC SDASEL[2..1]C[1:0] LDTDEN LFIC Receive Signal INSELC Monitor 10 RXDC[9:0] 10 10 INC1+ INC1– Clock & BISTSTC INC2+ Data INC2– Recovery RXCLKC+ PLL ÷2 ULCC RXCLKC– SPDSELC RXBISTC[1:0] RXPLLPDC RXRATEC Recovered Serial Data Recovered Character Clock ROE[2..1]C Reclocker ROUTC1+ ROE[2..1]C Output PLL ROUTC1– Clock Multiplier C ROUTC2+ ROUTC2– RECLKOC Character-Rate Clock C REPDOC TRGRATED x2
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CYV15G0404RB Device Configuration and Control Block Diagram = Internal Signal RXBIST[A..D] RXRATE[A..D] WREN SDASEL[A..D][1:0] Device Configuration RXPLLPD[A..D] ADDR[3:0] and Control Interface ROE[2..1][A..D] DATA[7:0] GLEN[11..0] FGLEN[2..0] Document #: 38-02102 Rev. *C Page 5 of 27 [+] Feedback
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CYV15G0404RB [1] Pin Configuration (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A IN ROUT IN ROUT IN ROUT IN ROUT IN ROUT IN ROUT IN ROUT IN ROUT V GND GND V CC CC C1– C1– C2– C2– D1– D1– D2– D2– A1– A1– A2– A2– B1– B1– B2– B2– B IN ROUT IN ROUT IN ROUT IN ROUT IN ROUT IN ROUT IN ROUT IN ROUT V GND GND V CC CC C1+ C1+ C2+ C2+ D1+ D1+ D2+ D2+ A1+ A1+ A2+ A2+ B1+ B1+ B2+ B2+ C TDI TMS INSELC INSELB ULCD ULCC DATA DATA DATA DATA SPD LDTD TRST TDO V GND GND V V GND CC CC CC [7] [5
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CYV15G0404RB [1] Pin Configuration (Bottom View) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ROUT IN ROUT IN ROUT IN ROUT IN ROUT IN ROUT IN ROUT IN ROUT IN V GND GND V CC CC A B2– B2– B1– B1– A2– A2– A1– A1– D2– D2– D1– D1– C2– C2– C1– C1– ROUT IN ROUT IN ROUT IN ROUT IN ROUT IN ROUT IN ROUT IN ROUT IN V GND GND V CC CC B B2+ B2+ B1+ B1+ A2+ A2+ A1+ A1+ D2+ D2+ D1+ D1+ C2+ C2+ C1+ C1+ TDO TRST LDTD SPD DATA DATA DATA DATA ULCC ULCD INSELB INSELC TMS TDI GND V V GND GND V CC CC CC C EN
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CYV15G0404RB Pin Definitions CYV15G0404RB Quad HOTLink II Deserializing Reclocker Name IO Characteristics Signal Description Receive Path Data and Status Signals RXDA[9:0] LVTTL Output, Parallel Data Output. RXDx[9:0] parallel data outputs change relative to the RXDB[9:0] synchronous to the receive interface clock. If RXCLKx± is a full-rate clock, the RXCLKx± clock outputs RXDC[9:0] RXCLK± output are complementary clocks operating at the character rate. The RXDx[9:0] outputs RXDD[9:0] for the
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CYV15G0404RB Pin Definitions (continued) CYV15G0404RB Quad HOTLink II Deserializing Reclocker Name IO Characteristics Signal Description LDTDEN LVTTL Input, Level Detect Transition Density Enable. When LDTDEN is HIGH, the Signal internal pull up Level Detector, Range Controller, and Transition Density Detector are all enabled to determine if the RXPLL tracks TRGCLKx± or the selected input serial data stream. If the Signal Level Detector, Range Controller, or Transition Density Detector are out
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CYV15G0404RB Pin Definitions (continued) CYV15G0404RB Quad HOTLink II Deserializing Reclocker Name IO Characteristics Signal Description DATA[7:0] LVTTL input Control Data Bus. The DATA[7:0] bus is the input data bus that configures the asynchronous, device. The WREN input writes the values of the DATA[7:0] bus into the latch [3] internal pull-up specified by address location on the ADDR[3:0] bus. Table 3, “Device Configu- ration and Control Latch Descriptions,” on page 14 lists the configura
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CYV15G0404RB Pin Definitions (continued) CYV15G0404RB Quad HOTLink II Deserializing Reclocker Name IO Characteristics Signal Description TDO 3-State LVTTL Output Test Data Out. JTAG data output buffer. High-Z while JTAG test mode is not selected. TDI LVTTL Input, Test Data In. JTAG data input port. internal pull up TRST LVTTL Input, JTAG reset signal. When asserted (LOW), this input asynchronously resets the internal pull up JTAG test access port controller. Power V +3.3V Power. CC GND Signal
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CYV15G0404RB operates at, or near the rate of the incoming data stream for in the selected serial data stream performs the clock extraction two primary cases: function. • When the incoming data stream resumes after a time in Each CDR accepts a character-rate (bit-rate÷10) or which it was “missing.” half-character-rate (bit-rate÷20) training clock from the associated TRGCLKx± input. This TRGCLKx± input is used to • When the incoming data stream is outside the acceptable signaling rate range.
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CYV15G0404RB reclocker serial drivers for a channel are in this disabled state, Power Control the associated internal reclocker logic also powers down. The deserialization logic and parallel outputs remain enabled. A The CYV15G0404RB supports user control of the powered up device reset (RESET sampled LOW) disables all output or down state of each transmit and receive channel. The drivers. RXPLLPDx latch controls the receive channels through the device configuration interface. RXPLLPDx = 0 disa
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CYV15G0404RB Latch Banks 12, 13, and 14 load values in the related latch latch banks. The S type contains those settings that normally banks in globally. A write operation to latch bank 12 performs do not change for a given application, whereas the D type a global write to latch banks 0, 3, 6, and 9, depending on the controls the settings that might change during the application's value of GLENx in these latch banks; latch bank 13 performs lifetime. The first and second rows of each channel (a
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CYV15G0404RB Table 3. Device Configuration and Control Latch Descriptions (continued) Name Signal Description RXPLLPDA Receive Channel Enable. The initialization value of the RXPLLPDx latch = 0. RXPLLPDx selects whether RXPLLPDB the associated receive channel is enabled or powered down. RXPLLPDx = 0 powers down the associated RXPLLPDC receive PLL and analog circuitry. RXPLLPDx = 1 enables the associated receive PLL and analog circuitry. RXPLLPDD RXBISTA[1:0] Receive Bist Disable / SMPTE Re
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CYV15G0404RB Table 4. Device Control Latch Configuration Table Reset ADDR Channel Type DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Value 0 A S 1 0 X X 0 0 RXRATEA GLEN0 10111111 (0000b) 1 A S SDASEL2A[1] SDASEL2A[0] SDASEL1A[1] SDASEL1A[0] X X TRGRATEA GLEN1 10101101 (0001b) 2 A D RXBISTA[1] RXPLLPDA RXBISTA[0] X ROE2A ROE1A X GLEN2 10110011 (0010b) 3 B S 1 0 X X 0 0 RXRATEB GLEN3 10111111 (0011b) 4 B S SDASEL2B[1] SDASEL2B[0] SDASEL1B[1] SDASEL1B[0] X X TRGRATEB GLEN4 10101101 (0100b) 5
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CYV15G0404RB JTAG controller does not enter any of the test modes after JTAG Support device power-up. In this JTAG reset state, the rest of the The CYV15G0404RB contains a JTAG port to allow system device will operate normally. level diagnosis of device interconnect. Of the available JTAG Note The order of device reset (using RESET) and JTAG modes, boundary scan and bypass are supported. This initialization does not matter. capability is present only on the LVTTL inputs and outputs and the TR
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CYV15G0404RB Figure 2. Receive BIST State Machine Monitor Data Receive BIST Received Detected LOW {BISTSTx, RXDx[0], RX PLL RXDx[1]} = Out of Lock BIST_START (101) {BISTSTx, RXDx[0], RXDx[1]} = BIST_WAIT (111) Start of BIST Detected No Yes, {BISTSTx, RXDx[0], RXDx[1]} = BIST_DATA_COMPARE (000, 001) Compare Next Character Mismatch {BISTSTx, RXDx[0], RXDx[1]} = Match BIST_DATA_COMPARE (000, 001) Auto-Abort Yes Condition No End-of-BIST End-of-BIST No State State Yes, {BISTSTx, RXDx[0], RXD
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CYV15G0404RB Static Discharge Voltage.......................................... > 2000 V Maximum Ratings (MIL-STD-883, Method 3015) Excedding maximum ratings may shorten the device life. User Latch Up Current .................................................... > 200 mA guidelines are not tested Power Up Requirements Storage Temperature ..................................–65°C to +150°C The CYV15G0404RB requires one power supply. The voltage Ambient Temperature with on any input or I/O pin cann
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CYV15G0404RB CYV15G0404RB DC Electrical Characteristics (continued) Parameter Description Test Conditions Min Max Unit Differential CML Serial Outputs: ROUTA1±, ROUTA2±, ROUTB1±, ROUTB2±, ROUTC1±, ROUTC2±, ROUTD1±, ROUTD2± V Output HIGH Voltage 100Ω differential load V – 0.5 V – 0.2 V OHC CC CC (V Referenced) CC 150Ω differential load V – 0.5 V – 0.2 V CC CC V Output LOW Voltage 100Ω differential load V – 1.4 V – 0.7 V OLC CC CC (V Referenced) CC 150Ω differential load V – 1.4 V – 0.7 V CC C
