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Cortex -R4 and Cortex-R4F
Revision: r1p3
Technical Reference Manual
Copyright © 2009 ARM Limited. All rights reserved.
ARM DDI 0363E (ID013010)
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Cortex-R4 and Cortex-R4F Technical Reference Manual Copyright © 2009 ARM Limited. All rights reserved. Release Information The following changes have been made to this book. Change History Date Issue Confidentiality Change 15 May 2006 A Confidential First release for r0p1 22 October 2007 B Non-Confidential First release for r1p2 16 June 2008 C Non-Confidential Restricted Access First release for r1p3 11 September 2009 D Non-Confidential Second release for r1p3 20 November 2009 E Non-Confidenti
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Contents Cortex-R4 and Cortex-R4F Technical Reference Manual Preface About this book ........................................................................................................ xvii Feedback .................................................................................................................. xxi Chapter 1 Introduction 1.1 About the processor ................................................................................................. 1-2 1.2 About the architecture
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Contents 2.10 Unaligned and mixed-endian data access support ................................................ 2-28 2.11 Big-endian instruction support ............................................................................... 2-29 Chapter 3 Processor Initialization, Resets, and Clocking 3.1 Initialization .............................................................................................................. 3-2 3.2 Resets ..............................................................
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Contents 11.4 Debug register descriptions ................................................................................. 11-10 11.5 Management registers ......................................................................................... 11-32 11.6 Debug events ....................................................................................................... 11-39 11.7 Debug exception ..................................................................................................
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Contents A.7 Dual core interface signals .................................................................................... A-16 A.8 Debug interface signals ......................................................................................... A-17 A.9 ETM interface signals ............................................................................................ A-19 A.10 Test signals ........................................................................................................
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List of Tables Cortex-R4 and Cortex-R4F Technical Reference Manual Change History ............................................................................................................................... ii Table 1-1 Configurable options ................................................................................................................. 1-13 Table 1-2 Configurable options at reset ................................................................................................
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List of Tables Table 4-16 Instruction Set Attributes Register 2 bit functions ..................................................................... 4-29 Table 4-17 Instruction Set Attributes Register 3 bit functions ..................................................................... 4-30 Table 4-18 Instruction Set Attributes Register 4 bit functions ..................................................................... 4-31 Table 4-19 Current Cache Size Identification Register bit functions ...
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List of Tables Table 8-6 Tag RAM bit descriptions, no parity or ECC ............................................................................. 8-26 Table 8-7 Cache sizes and tag RAM organization .................................................................................... 8-27 Table 8-8 Organization of a dirty RAM line ............................................................................................... 8-27 Table 8-9 Instruction cache data RAM sizes, no parity or ECC .......
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List of Tables Table 11-6 CP14 debug register map ....................................................................................................... 11-10 Table 11-7 Debug ID Register functions ................................................................................................... 11-11 Table 11-8 Debug ROM Address Register functions ................................................................................ 11-12 Table 11-9 Debug Self Address Offset Register functions ....
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List of Tables Table 14-5 QADD, QDADD, QSUB, and QDSUB instruction cycle timing behavior ................................... 14-9 Table 14-6 Media data-processing instructions cycle timing behavior ...................................................... 14-10 Table 14-7 Sum of absolute differences instruction timing behavior ......................................................... 14-11 Table 14-8 Example interlocks ................................................................................
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List of Tables Table A-18 FPU signals ............................................................................................................................... A-23 Table C-1 Differences between issue B and issue C .................................................................................. C-1 Table C-2 Differences between issue C and issue D .................................................................................. C-3 ARM DDI 0363E Copyright © 2009 ARM Limited. All rights
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List of Figures Cortex-R4 and Cortex-R4F Technical Reference Manual Key to timing diagram conventions .............................................................................................. xix Figure 1-1 Processor block diagram ............................................................................................................ 1-4 Figure 1-2 Processor Fetch and Decode pipeline stages .......................................................................... 1-17 Figure 1-3 Corte
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List of Figures Figure 4-16 Memory Model Feature Register 1 format ................................................................................ 4-23 Figure 4-17 Memory Model Feature Register 2 format ................................................................................ 4-24 Figure 4-18 Memory Model Feature Register 3 format ................................................................................ 4-25 Figure 4-19 Instruction Set Attributes Register 0 format ................
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List of Figures Figure 11-3 Debug ROM Address Register format .................................................................................... 11-12 Figure 11-4 Debug Self Address Offset Register format ............................................................................ 11-13 Figure 11-5 Debug Status and Control Register format ............................................................................. 11-14 Figure 11-6 Watchpoint Fault Address Register format ....................
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Preface This preface introduces the Cortex-R4 and Cortex-R4F Technical Reference Manual. It contains the following sections: • About this book on page xvii • Feedback on page xxi. ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. xvi ID013010 Non-Confidential, Unrestricted Access
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Preface About this book This is the Technical Reference Manual (TRM) for the Cortex-R4 and Cortex-R4F processors. In this book the generic term processor means both the Cortex-R4 and Cortex-R4F processors. Any differences between the two processors are described where necessary. Note The Cortex-R4F process o r is a Cortex-R4 processor that includes the optional Floating Point Unit (FPU) extension, see Product revision information on page 1-24 for more information. In this book, references t
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Preface Read this for a description of the Memory Protection Unit (MPU) and the access permissions process. Chapter 8 Level One Memory System Read this for a description of the Level One (L1) memory system. Chapter 10 Power Control Read this for a description of the power control facilities. Chapter 11 Debug Read this for a description of the debug support. Chapter 12 FPU Programmer’s Model Read this for a description of the Floating Point Unit (FPU) support in the Cortex-R4F processor. C
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Preface monospace Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code. monospace Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name. monospace italic Denotes arguments to monospace text where the argument is to be replaced by a specific value. monospace bold Denotes language keywords when used outside example code. < and > Enclose replaceable terms for as
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Preface Prefix R Denotes AXI read data channel signals. Prefix W Denotes AXI write data channel signals. Further reading This section lists publications by ARM and by third parties. See http://infocenter.arm.com for access to ARM documentation. ARM publications This book contains information that is specific to the processor. See the following documents for other relevant information: ® • AMBA AXI Protocol Specification (ARM IHI 0022) • AMBA 3 APB Protocol Specification (ARM IHI 0024) • ARM Ar
