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® ®
Intel StrongARM SA-1100
Microprocessor
Developer’s Manual
August 1999
Order Number: 278088-004
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Contents 1 Introduction......................................................................................................................1-1 1.1 Intel® StrongARM® SA-1100 Microprocessor .................................................. 1-1 1.2 Overview............................................................................................................ 1-4 1.3 Example System................................................................................................ 1-5 1.4 ARM™ Ar
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5.2.11 Registers 10 – 12 RESERVED............................................................. 5-6 5.2.12 Register 13 – Process ID Virtual Address Mapping.............................. 5-7 5.2.13 Register 14 – Debug Support (Breakpoints)......................................... 5-8 5.2.14 Register 15 – Test, Clock, and Idle Control.......................................... 5-9 6 Caches, Write Buffer, and Read Buffer...........................................................................6-1 6.
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9 System Control Module...................................................................................................9-1 9.1 General-Purpose I/O.......................................................................................... 9-1 9.1.1 GPIO Register Definitions..................................................................... 9-2 9.1.1.1 GPIO Pin-Level Register (GPLR) ............................................ 9-3 9.1.1.2 GPIO Pin Direction Register (GPDR) ....................
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9.5.3.6 Booting After Sleep Mode...................................................... 9-29 9.5.3.7 Reviving the DRAMs from Self-Refresh Mode ...................... 9-30 9.5.4 Notes on Power Supply Sequencing .................................................. 9-30 9.5.5 Assumed Behavior of an SA-1100 System in Sleep Mode................. 9-30 9.5.6 Pin Operation in Sleep Mode.............................................................. 9-32 9.5.7 Power Manager Registers ........................
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10.5.3 DRAM Access Followed by a Refresh Operation............................. 10-25 10.6 PCMCIA Overview........................................................................................ 10-26 10.6.1 32-Bit Data Bus Operation............................................................... 10-27 10.6.2 External Logic for PCMCIA Implementation ................................... 10-28 10.6.3 PCMCIA Interface Timing Diagrams and Parameters ..................... 10-31 10.7 Initialization of
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11.7.5.1Lines Per Panel (LPP) ......................................................... 11-36 11.7.5.2Vertical Sync Pulse Width (VSW)........................................ 11-36 11.7.5.3End-of-Frame Line Clock Wait Count (EFW)....................... 11-37 11.7.5.4Beginning-of-Frame Line Clock Wait Count (BFW)............. 11-37 11.7.6 LCD Controller Control Register 3.................................................... 11-39 11.7.6.1Pixel Clock Divider (PCD)....................................
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11.8.3.1UDC Disable (UDD)............................................................. 11-64 11.8.3.2 UDC Active (UDA) .............................................................. 11-64 11.8.3.3Bit 2 Reserved ..................................................................... 11-64 11.8.3.4Endpoint 0 Interrupt Mask (EIM).......................................... 11-64 11.8.3.5Receive Interrupt Mask (RIM)............................................. 11-64 11.8.3.6Transmit Interrupt Mask (TI
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11.9.1.5Data Field ............................................................................ 11-81 11.9.1.6CRC Field ............................................................................ 11-81 11.9.1.7Baud Rate Generation......................................................... 11-81 11.9.1.8Receive Operation............................................................... 11-82 11.9.1.9Transmit Operation.............................................................. 11-83 11.9.1.10Simult
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11.9.9.5Receive Transition Detect Status (RTD) (read/write, noninterruptible)................................................ 11-99 11.9.9.6End of Frame Flag (EOF) (read-only, noninterruptible)................................................. 11-99 11.9.9.7CRC Error Status (CRE) (read-only, noninterruptible)............................................... 11-100 11.9.9.8Receiver Overrun Status (ROR) (read-only, noninterruptible)............................................... 11-100 11.9.10 UAR
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11.10.10.4Transmit FIFO Service Request Flag (TFS) (read-only, maskable interrupt).......................................... 11-122 11.10.10.5Receive FIFO Service Request Flag (RFS) (read-only, maskable interrupt).......................................... 11-122 11.10.10.6Framing Error Status (FRE) (read/write, nonmaskable interrupt)................................... 11-123 11.10.11HSSP Status Register 1 ................................................................ 11-124 11.10.11.1Receive
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11.11.7.2Receive FIFO Service Request Flag (RFS) (read-only, maskable interrupt).......................................... 11-139 11.11.7.3Receiver Idle Status (RID) (read/write, maskable interrupt) ......................................... 11-140 11.11.7.4Receiver Begin of Break Status (RBB) (read/write, nonmaskable interrupt) ................................... 11-140 11.11.7.5Receiver End of Break Status (REB) (read/write, nonmaskable interrupt)11-140 11.11.7.6Error in FIFO Flag (EIF) (rea
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11.12.6.1Audio Transmit FIFO Service Request Flag (ATS) (read-only, maskable interrupt).......................................... 11-163 11.12.6.2Audio Receive FIFO Service Request Flag (ARS) (read-only, maskable interrupt).......................................... 11-163 11.12.6.3Telecom Transmit FIFO Service Request Flag (TTS) (read-only, maskable interrupt).......................................... 11-164 11.12.6.4Telecom Receive FIFO Service Request Flag (TRS) (read-only, maskable interrup
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11.12.12.1Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible)............................................... 11-181 11.12.12.2Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptibl11-181 11.12.12.3SSP Busy Flag (BSY) (read-only, noninterruptible)............................................... 11-181 11.12.12.4Transmit FIFO Service Request Flag (TFS) (read-only, maskable interrupt)............................................ 1-181 11.12.12.5Receive FIFO Service Request Flag (R
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16.4 Instruction Register.......................................................................................... 16-2 16.5 Public Instructions ........................................................................................... 16-2 16.5.1 EXTEST (00000) ................................................................................ 16-3 16.5.2 SAMPLE/PRELOAD (00001) ............................................................. 16-3 16.5.3 CLAMP (00100)................................
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Figures 1-1 SA-1100 Features.............................................................................................. 1-1 1-2 SA-1100 Example System................................................................................. 1-5 2-1 SA-1100 Block Diagram .................................................................................... 2-2 2-2 SA-1100 Functional Diagram............................................................................. 2-3 2-3 SA-1100 Memory Map............
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11-24 HP-SIR Modulation Example....................................................................... 11-104 11-25 UART Frame Format for IrDA Transmission (<= 115.2 Kbps) .................... 11-105 11-26 4PPM Modulation Encodings ...................................................................... 11-105 11-27 4PPM Modulation Example ......................................................................... 11-106 11-28 High-Speed Serial Frame Format for IrDA Transmission (4.0 Mbps)..........
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10-5 DRAM Memory Size Options......................................................................... 10-14 10-6 DRAM Row/Column Address Multiplexing .................................................... 10-14 11-1 Peripheral Control Modules’ Register Width and DMA Port Size .................... 11-2 11-2 Peripheral Units’ Base Addresses ................................................................... 11-3 11-3 Peripheral Units’ Interrupt Numbers ..............................................
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